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    Submersible electronic sensor
    71.
    发明授权
    Submersible electronic sensor 有权
    潜水电子传感器

    公开(公告)号：US08887576B2

    公开(公告)日：2014-11-18

    申请号：US13429253

    申请日：2012-03-23

    Applicant: Joe Castagna

    Inventor： Joe Castagna

    IPC: G01L9/00

    CPC classification number: G01L9/00 ,  F16J15/064 ,  G01D11/245 ,  G01D11/26 ,  G01L19/0084 ,  G01L19/0672 ,  G01L19/143 ,  G01L19/148 ,  G01L19/149 ,  H05K1/0296 ,  H05K1/118 ,  H05K2201/09736 ,  H05K2201/09781

    Abstract: The invention provides a submersible, electrically-powered sensor assembly that incorporates a flexible seal assembly having operative and non-operative electrical traces of a uniform vertical height for carrying clamping loads and avoiding signal loss along a signal carrying trace due to compression of the flex seal, minimizing fluid leak paths between two flange surfaces, providing stability in compression, and enabling electrical communication in an environment having an operating fluid.

    Abstract translation: 本发明提供了一种潜水电动传感器组件，其包括柔性密封组件，其具有用于承载夹紧负载的均匀垂直高度的操作和非操作电迹线，并且避免了由于柔性密封件的压缩而沿着信号承载痕迹的信号损失 使两个法兰表面之间的流体泄漏路径最小化，提供压缩稳定性，以及在具有工作流体的环境中实现电通信。

    CIRCUIT BOARD STRUCTURE
    72.
    发明申请
    CIRCUIT BOARD STRUCTURE 审中-公开
    电路板结构

    公开(公告)号：US20140311775A1

    公开(公告)日：2014-10-23

    申请号：US14144522

    申请日：2013-12-30

    Applicant: HON HAI PRECISION INDUSTRY CO., LTD. ,  HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD

    Inventor： CHAO-RONG LAI

    IPC: H05K1/11

    CPC classification number: H05K3/3447 ,  H05K1/116 ,  H05K3/3468 ,  H05K2201/09781 ,  H05K2203/044 ,  H05K2203/046

    Abstract: A circuit board structure includes a circuit board and at least one adsorption strip set on the circuit board. The circuit board defines at least one group of pin holes arranged along a predetermined line to receive a number of pins of an electronic component. The adsorption strip absorbs excess conducting material between adjacent pins during a wave-soldering process.

    Abstract translation: 电路板结构包括电路板和在电路板上设置的至少一个吸附条。 电路板限定沿着预定线布置的至少一组针孔，以接收电子部件的多个销。 吸波带在波峰焊过程中吸收相邻引脚之间的过量导电材料。

    METHOD OF EMBEDDING A PRE-ASSEMBLED UNIT INCLUDING A DEVICE INTO A FLEXIBLE PRINTED CIRCUIT AND CORRESPONDING ASSEMBLY
    74.
    发明申请
    METHOD OF EMBEDDING A PRE-ASSEMBLED UNIT INCLUDING A DEVICE INTO A FLEXIBLE PRINTED CIRCUIT AND CORRESPONDING ASSEMBLY 有权
    将包括设备的预组装单元嵌入柔性印刷电路和对应组件的方法

    公开(公告)号：US20140268594A1

    公开(公告)日：2014-09-18

    申请号：US13835845

    申请日：2013-03-15

    Applicant: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC. ,  Power Gold LLC

    Inventor： James Jen-Ho WANG ,  Jin Joo PARK ,  Masahiko KOUCHI

    IPC: H05K1/02 ,  H05K13/04

    CPC classification number: H05K1/189 ,  H01L2224/83192 ,  H05K1/0207 ,  H05K1/183 ,  H05K2201/09781 ,  H05K2201/10681 ,  Y10T29/49146

    Abstract: A flexible printed circuit assembly, having a first flexible printed circuit having a first conductive layer and a device that is connected the first conductive layer; and a second flexible printed circuit having a second conductive layer, an insulating center layer, and a third conductive layer, the insulating center layer arranged in-between the second and the third conductive layers, the second conductive layer and the insulating center layer being removed to form an opening to expose an upper surface of the third conductive layer, wherein the first flexible printed circuit is arranged such that the device is accommodated inside the opening, a lower surface of the device being in thermal connection with the third conductive layer, and the first conductive layer is arranged to be in electrical connection with the second conductive layer.

    Abstract translation: 一种柔性印刷电路组件，具有具有第一导电层的第一柔性印刷电路和连接第一导电层的器件; 以及第二柔性印刷电路，其具有第二导电层，绝缘中心层和第三导电层，所述绝缘中心层布置在所述第二和第三导电层之间，所述第二导电层和所述绝缘中心层被去除 以形成用于暴露第三导电层的上表面的开口，其中第一柔性印刷电路被布置成使得该装置容纳在开口内部，该装置的下表面与第三导电层热连接，以及 第一导电层被布置成与第二导电层电连接。

    Display device comprising a plurality of upper-layer lines with exposed upper surfaces which are not covered, a plurality of lower-layer lines, and a plurality of adjustment layers
    77.
    发明授权
    Display device comprising a plurality of upper-layer lines with exposed upper surfaces which are not covered, a plurality of lower-layer lines, and a plurality of adjustment layers 有权
    显示装置包括具有未被覆盖的暴露的上表面的多个上层线，多个下层线以及多个调整层

    公开(公告)号：US08760611B2

    公开(公告)日：2014-06-24

    申请号：US12749627

    申请日：2010-03-30

    Applicant: Masashi Sato

    Inventor： Masashi Sato

    IPC: G02F1/1345 ,  G02F1/1333

    CPC classification number: H05K1/117 ,  G02F1/1345 ,  G02F2001/136254 ,  H05K3/4644 ,  H05K2201/09672 ,  H05K2201/09781 ,  H05K2203/162

    Abstract: A display device at which the contact-type wiring inspection can be accurately carried out is provided. In a display device in which two or more kinds of lines are arranged on a substrate by way of an interlayer insulation film, in at least a partial region of the substrate outside a display region, a plurality of upper-layer lines which are arranged parallel to each other on an upper side of the interlayer insulation film, lower-layer lines which are arranged on a lower side of the interlayer insulation film and between the upper-layer lines or adjacent to the upper-layer lines, and adjustment layers for adjusting a height which are arranged on a lower side of the interlayer insulation film and below the upper-layer lines so as to position surfaces of the upper-layer lines at a highest position on the substrate are formed.

    Abstract translation: 提供可以精确地进行接触式接线检查的显示装置。 在其中通过层间绝缘膜在基板上布置两种或更多种线的显示装置中，在显示区域外的基板的至少部分区域中，布置成平行的多条上层线 在层间绝缘膜的上侧彼此相对，布置在层间绝缘膜的下侧，上层线之间或与上层线相邻的下层线，以及用于调节的调整层 形成布置在层间绝缘膜的下侧并在上层线下方的高度，以便将上层线的表面定位在基板上的最高位置。

    PRINTED CIRCUIT BOARD
    79.
    发明申请
    PRINTED CIRCUIT BOARD 有权
    印刷电路板

    公开(公告)号：US20140060892A1

    公开(公告)日：2014-03-06

    申请号：US14016348

    申请日：2013-09-03

    Applicant: YAZAKI CORPORATION

    Inventor： Yasushi Katayama

    IPC: H05K1/02

    CPC classification number: H05K1/0271 ,  H05K3/0005 ,  H05K2201/09227 ,  H05K2201/0969 ,  H05K2201/09781

    Abstract: A printed circuit board is designed to meet the following requirements. A front-back copper foil residual rate difference a−b falls within a range of −10% to 10%, where the insulative board is divided into a plurality of divisions, in which front and back surface copper foil residual rates of each division are a % and b %, respectively. A difference (a−b)−(c−d) between front-back copper foil residual rate differences of adjacent divisions falls within a range of −10% to 10%, where the front and back surface copper foil residual rates of a division adjacent to the each division are c % and d %, respectively. There are not three or more consecutive divisions for which the difference between the front-back copper foil residual rate differences goes beyond a range of −5% to 5%.

    Abstract translation: 印刷电路板设计符合以下要求。 前后铜箔剩余率差ab在-10％〜10％的范围内，其中绝缘板分成多个部分，其中每个部分的前后铜箔残留率为％ 和b％。 相邻部分的前后铜箔残留率差异（ab） - （cd）在-10％至10％的范围内，其中与每个相邻部分相邻的划分的前后铜箔残留率 分别为c％和d％。 前后铜箔剩余率差异之间的差异不超过-5％至5％的范围，不存在三个以上的连续分割。

    Interposer having a defined through via pattern
    80.
    发明授权
    Interposer having a defined through via pattern 有权
    内插器具有定义的通孔图案

    公开(公告)号：US08664768B2

    公开(公告)日：2014-03-04

    申请号：US13463474

    申请日：2012-05-03

    Applicant: Shih-Wei Liang ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Chia-Chun Miao ,  Chun-Lin Lu

    Inventor： Shih-Wei Liang ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Chia-Chun Miao ,  Chun-Lin Lu

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/053 ,  H01L23/12

    CPC classification number: H01L23/485 ,  G06F17/5068 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/115 ,  H05K2201/068 ,  H05K2201/09781 ,  H05K2201/10378

    Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.

    Abstract translation: 一种结构包括具有多个球的衬底，半导体芯片和电连接衬底和半导体芯片的插入器。 所述插入器包括第一侧，与所述第一侧相对的第二侧，至少一个第一排除区域，所述至少一个第一排除区域延伸穿过所述多个球的每个球上方的所述插入器，至少一个主动通孔，其从所述插入件的第一侧延伸到 其中所述至少一个活性通孔形成在所述至少一个第一排除区域的外部，并且其中在所述至少一个第一排除区域内没有形成活性通孔，以及至少一个虚拟通孔， 所述插入器的第一侧到所述插入件的第二侧，其中所述至少一个虚拟通孔形成在所述至少一个第一排除区域内。

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