公开(公告)号：US20050235490A1

公开(公告)日：2005-10-27

申请号：US10832321

申请日：2004-04-27

Applicant: Chih-Chung Chen

Inventor： Chih-Chung Chen

IPC: H05K1/00 ,  H05K1/02 ,  H05K3/00 ,  H05K3/22

CPC classification number: H05K3/0052 ,  H05K1/0269 ,  H05K3/225 ,  H05K2201/09145 ,  H05K2201/09845 ,  H05K2201/10204 ,  H05K2201/10598 ,  H05K2203/0143 ,  H05K2203/0191 ,  H05K2203/0228 ,  H05K2203/0278 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49135 ,  Y10T29/49718 ,  Y10T29/49721 ,  Y10T29/49723 ,  Y10T29/49725 ,  Y10T29/49726 ,  Y10T29/4973 ,  Y10T29/49732 ,  Y10T29/49734 ,  Y10T29/4975

Abstract: A printed circuit board defective area transplant repair method in which printed circuit boards that are determined to be defective undergo a series of reworking procedures comprised of plotting the printed circuit board area block plan, selecting the printed circuit boards, cutting out the area blocks, cutting the selected area blocks, applying the adhesive and fitting area blocks, adjusting the area block alignment, roller tamping the plastic band, curing the adhesive, and tearing off the plastic band. Following the reworking operations, defective printed circuit boards are restored into a good products capable of continuous use such that printed circuit board fabrication and production is even more economical and environmentally protective and, furthermore, printed circuit board manufacturing reaches maximum utilization rates, thereby effectively increasing practical production value.

Abstract translation: 一种印刷电路板缺陷区域移植修复方法，其中确定为有缺陷的印刷电路板经历一系列返工程序，其包括绘制印刷电路板区域块图，选择印刷电路板，切割区域块，切割 所选区域块，涂抹粘合剂和装配区域块，调整区域块对齐，辊夯塑料带，固化粘合剂，撕下塑料带。 在返工操作之后，有缺陷的印刷电路板被恢复成能够连续使用的良好产品，使得印刷电路板的制造和生产更加经济和环境保护，此外，印刷电路板制造达到最大利用率，从而有效地增加 实用生产价值。

公开(公告)号：US06787711B2

公开(公告)日：2004-09-07

申请号：US10195547

申请日：2002-07-16

Applicant: Shunichi Kikuchi ,  Mitsutaka Yamada ,  Kenji Iketaki

Inventor： Shunichi Kikuchi ,  Mitsutaka Yamada ,  Kenji Iketaki

IPC: H05K111

CPC classification number: H05K1/0209 ,  H05K1/0201 ,  H05K3/3494 ,  H05K2201/066 ,  H05K2201/09781 ,  H05K2201/10204 ,  H05K2203/1121 ,  H05K2203/304 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A printed wiring board device includes circuit parts which are mounted on a wiring board and constitute parts of a circuit in the printed wiring board device. Pads are provided on the wiring board in the circumference of the circuit parts, and the pads being electrically isolated from the circuit. Heat-absorbing dummy parts are mounted on the pads, and the dummy parts absorb heat from the circuit parts through the pads during reflow soldering.

Abstract translation: 印刷电路板装置包括安装在布线板上并构成印刷线路板装置中的电路的一部分的电路部分。 在电路部分的圆周上的布线板上设置有焊盘，并且焊盘与电路电隔离。 吸热虚拟部件安装在焊盘上，并且虚拟部件在回流焊接期间通过焊盘吸收来自电路部件的热量。

公开(公告)号：US20040165361A1

公开(公告)日：2004-08-26

申请号：US10788463

申请日：2004-03-01

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Suzushi Kimura ,  Tsuyoshi Himori ,  Koji Hashimoto

IPC: H05K001/18

CPC classification number: H05K1/184 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/19103 ,  H01L2924/19105 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4046 ,  H05K3/4602 ,  H05K2201/09118 ,  H05K2201/09827 ,  H05K2201/10204 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/161 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49172

Abstract: The invention relates to a module component having chip components buried in a circuit board, and a method of manufacturing the same, and more specifically it relates to a module component capable of obtaining desired circuit characteristics and functions stably if the size of the component is reduced, being produced very efficiently, and suited to machine mounting, and a method of manufacturing the same. According to the invention, since a desired circuit is composed by disposing a specific number of chip components according to a specified rule, it is not necessary to heat the buried chip components at high temperature when forming a module, chip components are obtained in specified values, and the circuit characteristics, functions, and dimensional precision are stably obtained exactly as designed, and moreover since the chip components are disposed according to a specified rule, it is easy to automate insertion of chip components and increase its operation speed, even if the size of the chip components is reduced, and the circuit composition may be flexibly and easily changed only by changing the inserting position and type of chip components.

公开(公告)号：US20030011098A1

公开(公告)日：2003-01-16

申请号：US10201416

申请日：2002-07-22

Inventor： Charles W. Lewis ,  Jesse Pedigo ,  Joseph Schug

IPC: B28B001/48

CPC classification number: H05K3/1233 ,  H05K3/4053 ,  H05K3/4069 ,  H05K2201/10204 ,  H05K2203/0126 ,  H05K2203/0156 ,  H05K2203/0182 ,  H05K2203/0554 ,  Y10T29/49165

Abstract: Methods for improved electronic substrate via and thru-hole filling, particularly through the use of drilled stand-offs formed by control-depth drilling oversized non-thru-holes and the use of inserted support pillars to prevent sagging of the substrate during filling. In particular, through the use of: (1) a via fill stand off adapted for use with a substrate comprising at least two via holes to be filled, each of the via holes having a diameter of X mils, the standoff comprising at least one recess formed by control-depth drilling of holes having a diameter at least 12X mils; and (2) a via fill standoff adapted for use with a substrate comprising at least one via hole to be filled, the standoff comprising: at least one recess; and at least one support pillar positioned within the recess wherein the support pillar is not an integral part of the standoff.

Abstract translation: 用于改进电子基板通孔和通孔填充的方法，特别是通过使用通过控制深度钻孔超大非贯穿孔形成的钻孔支座以及使用插入的支撑柱来防止在填充期间底板的松弛。 特别地，通过使用：（1）适于与包括至少两个要填充的通孔的基板一起使用的通孔填充支架，每个通孔具有X密耳的直径，所述支座包括至少一个 通过直径至少为12X密耳的孔的控制深度钻孔形成的凹陷; 和（2）适于与包括要填充的至少一个通孔的基板一起使用的通孔填充支座，所述支座包括：至少一个凹部; 以及定位在所述凹部内的至少一个支撑柱，其中所述支撑柱不是所述支座的组成部分。

公开(公告)号：US6131277A

公开(公告)日：2000-10-17

申请号：US360788

申请日：1999-07-26

Applicant: Jonathan Cadenhead ,  Terry Richard Fleegle ,  Michael Carlos Menard

Inventor： Jonathan Cadenhead ,  Terry Richard Fleegle ,  Michael Carlos Menard

IPC: H05K3/34 ,  H05K3/36 ,  H05K3/40

CPC classification number: H01R12/62 ,  H05K3/363 ,  H05K2201/10204 ,  H05K2201/10242 ,  H05K2203/167 ,  H05K3/341 ,  H05K3/4015 ,  Y10S439/931 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: An electrical circuit includes a substrate having at least two alignment pads on the substrate that are accurately aligned with a first set of electrical interconnect pads, and also includes a corresponding number of alignment posts that are cylindrical and have flat bases that are geometrically similar to and smaller than a corresponding shape of each of the at least two alignment pads by a predetermined solder fillet radius. Each of the at least two alignment posts is reflow soldered to one of the at least two alignment pads. An electrical part can be accurately aligned to the substrate using the alignment posts, during attachment of the electrical part.

Abstract translation: 电路包括具有至少两个对准焊盘的衬底，衬底上的至少两个对准焊盘与第一组电互连衬垫精确对准，并且还包括相应数量的对准柱，其为圆柱形并且具有几何等同于 小于所述至少两个对准焊盘中的每一个的相应形状，并通过预定的焊料圆角半径。 所述至少两个对准柱中的每一个被回流焊接到所述至少两个对准焊盘中的一个。 在电气部件的附接期间，可以使用对准柱将电气部件精确地对准到基板。

公开(公告)号：US5116440A

公开(公告)日：1992-05-26

申请号：US475945

申请日：1990-02-06

Applicant: Kazunori Takeguchi ,  Kohji Hirata

Inventor： Kazunori Takeguchi ,  Kohji Hirata

IPC: B32B37/18 ,  H05K1/18 ,  H05K3/46

CPC classification number: B32B37/182 ,  B32B37/0023 ,  H05K3/4697 ,  B29L2031/3425 ,  B32B2457/08 ,  H05K1/182 ,  H05K1/183 ,  H05K2201/0133 ,  H05K2201/0355 ,  H05K2201/10204 ,  H05K2203/063 ,  H05K2203/1147

Abstract: In manufacturing multilayer printed wiring boards with a cavity for mounting an electronic device, a rubber or composite rubber sheet is mounted in the cavity to prevent a prepreg resin from flowing into the cavity. The rubber sheet or composite rubber sheet is removed after applying pressure and temperature to an assembly consisting of boards to be bonded and the prepreg between them. This eliminates poor bonding which can result when resin flows into the cavity.

Abstract translation: 在制造具有用于安装电子装置的空腔的多层印刷线路板中，橡胶或复合橡胶片安装在空腔中以防止预浸料树脂流入空腔。 在将压力和温度施加到由待粘合的板和它们之间的预浸料组成的组件之后，将橡胶片或复合橡胶片除去。 这消除了当树脂流入空腔时可能导致的不良粘合。

公开(公告)号：US3238624A

公开(公告)日：1966-03-08

申请号：US17941462

申请日：1962-03-13

Applicant: MELPAR INC

Inventor： MCCABE PHILIP J

IPC: B23B35/00 ,  B23Q35/02 ,  H05K3/00

CPC classification number: B23B35/005 ,  B23Q35/02 ,  H05K3/0002 ,  H05K3/0008 ,  H05K3/005 ,  H05K2201/10204 ,  H05K2203/056 ,  Y10T408/08

公开(公告)号：US20230300987A1

公开(公告)日：2023-09-21

申请号：US18175898

申请日：2023-02-28

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Masahiro KYOZUKA

IPC: H05K3/00 ,  H05K1/05

CPC classification number: H05K3/0011 ,  H05K1/05 ,  H05K2201/10204 ,  H05K2201/093 ,  H05K2201/09372

Abstract: A wiring board includes a first insulating layer, a pad formed on one surface of the first insulating layer, a second insulating layer, formed on the one surface of the first insulating layer, and including an opening exposing the pad, and a reinforcing metal layer formed in contact with the first insulating layer, and provided around the pad so as to be separated from the pad in a plan view. The pad is disposed inside the opening without making contact with the second insulating layer. An end, on a side of the first insulating layer, in a portion of an inner side surface of the opening of the second insulating layer makes contact with the reinforcing metal layer, and an end in another portion of the inner side surface of the opening of the second insulating layer makes contact with the one surface of the first insulating layer.

公开(公告)号：US09980374B2

公开(公告)日：2018-05-22

申请号：US15033836

申请日：2014-10-24

Applicant: INGENICO GROUP

Inventor： Stephane Pavageau ,  Xavier Lambert

IPC: H05K7/00 ,  H05K1/02 ,  G06K7/00 ,  G06F21/86 ,  B23K1/00 ,  H05K3/10 ,  H05K3/34 ,  H05K3/12 ,  H05K3/14 ,  H05K3/24 ,  B23K101/42

CPC classification number: H05K1/0284 ,  B23K1/0016 ,  B23K2101/42 ,  G06F21/86 ,  G06K7/0091 ,  H05K1/0275 ,  H05K3/10 ,  H05K3/1241 ,  H05K3/1275 ,  H05K3/143 ,  H05K3/245 ,  H05K3/34 ,  H05K2201/09409 ,  H05K2201/09781 ,  H05K2201/098 ,  H05K2201/10204 ,  H05K2203/0551

Abstract: A support is provided for fabrication of an electronic device. The support includes at least one component to be protected and at least one three-dimensional element of a height at least equal to a height of the electronic component. The three-dimensional element is disposed laterally opposite the at least one component to be protected. The three-dimensional element is chiefly constituted of a permanent assembling material.

公开(公告)号：US09966333B2

公开(公告)日：2018-05-08

申请号：US15725144

申请日：2017-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H05K1/11 ,  H05K1/16 ,  H05K1/09 ,  H05K1/03 ,  H05K7/00 ,  H05K1/18 ,  H01L23/498 ,  H05K1/02 ,  H01L21/48 ,  H05K3/00 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: (1) a first dielectric structure having a first surface and a second surface opposite the first surface; (2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; (3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and (4) a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including at least one conductive trace, wherein the first dielectric structure defines at least one opening, and a periphery of the opening corresponds to a periphery of the through hole of the second dielectric structure.