公开(公告)号：US07091619B2

公开(公告)日：2006-08-15

申请号：US10805499

申请日：2004-03-19

Applicant: Akiyoshi Aoyagi

Inventor： Akiyoshi Aoyagi

IPC: H01L23/02

CPC classification number: H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A method is provided to enhance the connection reliability in three-dimensional mounting while considering the warping of packages. Opening diameters of the openings provided corresponding to protruding electrodes, respectively, are set so as to gradually decrease from the central portion toward the outer peripheral portion of a carrier substrate, and the opening diameters of openings provided corresponding to the protruding electrodes, respectively, are set so as to gradually decrease from the central portion toward the outer peripheral portion of another carrier substrate.

Abstract translation: 提供了一种在考虑包装翘曲的同时增强三维安装中的连接可靠性的方法。 分别对应于突出电极设置的开口的开口直径被设定为从载体基板的中心部分朝向外周部分逐渐减小，并且分别对应于突出电极设置的开口的开口直径为 被设定为从另一个载体基板的中央部朝向外周部逐渐减小。

公开(公告)号：US07057272B2

公开(公告)日：2006-06-06

申请号：US10986151

申请日：2004-11-12

Applicant: Masateru Koide

Inventor： Masateru Koide

IPC: H01L23/52 ,  H01L23/48

CPC classification number: H05K1/0263 ,  H01L23/32 ,  H01L23/367 ,  H01L23/50 ,  H01L23/5385 ,  H01L25/162 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K2201/10189 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: A package substrate has a power supply path different from a signal supply path to a semiconductor element. A semiconductor element is mounted on a first surface of the package substrate. A second surface opposite to the first surface is provided with external connection terminals. A power supply layer is formed inside the package substrate. The package substrate has electrode terminals provided in a part other than the second surface. The electrode terminals are connected to the power supply layer.

Abstract translation: 封装衬底具有不同于到半导体元件的信号提供路径的电源路径。 半导体元件安装在封装基板的第一表面上。 与第一表面相对的第二表面设置有外部连接端子。 电源层形成在封装衬底的内部。 封装基板具有设置在第二表面以外的部分的电极端子。 电极端子连接到电源层。

公开(公告)号：US07027308B2

公开(公告)日：2006-04-11

申请号：US10444989

申请日：2003-05-27

Applicant: Jin-Kwon Park ,  Chan-youn Won

Inventor： Jin-Kwon Park ,  Chan-youn Won

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0246 ,  H01R12/721 ,  H01R13/658 ,  H05K1/0231 ,  H05K1/14 ,  H05K7/1429 ,  H05K2201/044 ,  H05K2201/10022 ,  H05K2201/10189 ,  H05K2201/1053

Abstract: A PCB having a card slot receiving a card provided with signal input/output pins and a circuit element to provide extended capability is inserted, and having data transmission pins, a power pin and a ground pin in correspondence to the signal input/output pins, comprises an electronic device internally provided for impedance matching with the card, and having a first end connected to one of the data transmission pins and a second end connected to one of the power pin and the ground pin. With this configuration, a card slot internally comprises an electronic device for impedance matching, so that a space of the PCB can be efficiently utilized.

Abstract translation: 插入具有接收设置有信号输入/输出引脚的卡的卡插槽和提供扩展能力的电路元件的PCB，并且具有对应于信号输入/输出引脚的数据传输引脚，电源引脚和接地引脚， 包括内部提供用于与卡的阻抗匹配的电子设备，并且具有连接到数据传输引脚之一的第一端和连接到电源引脚和接地引脚之一的第二端。 利用这种配置，卡槽内部包括用于阻抗匹配的电子设备，从而可以有效地利用PCB的空间。

公开(公告)号：US20060018104A1

公开(公告)日：2006-01-26

申请号：US11080672

申请日：2005-03-16

Applicant: Hiroki Katayama ,  Yoshiaki Ishigami

Inventor： Hiroki Katayama ,  Yoshiaki Ishigami

IPC: H05K7/06

CPC classification number: H05K3/3442 ,  H05K1/0239 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/09072 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10121 ,  H05K2201/10484 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10984 ,  H05K2201/2036 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic component mounted structure has: a circuit board; two semiconductor elements that are mounted on the circuit board; and an AC coupling capacitor that is operable to cut off signals with a predetermined frequency or less and is provided between the two semiconductor elements. The AC coupling capacitor is mounted on the circuit board such that a part or a whole of the AC coupling capacitor is away from the surface of the circuit board.

Abstract translation: 电子部件安装结构具有：电路板; 安装在电路板上的两个半导体元件; 以及AC耦合电容器，其可操作以以预定频率或更小的频率切断信号，并且设置在两个半导体元件之间。 AC耦合电容器安装在电路板上，使得AC耦合电容器的一部分或全部远离电路板的表面。

公开(公告)号：US06977440B2

公开(公告)日：2005-12-20

申请号：US10454029

申请日：2003-06-04

Applicant: L. Elliott Pflughaupt ,  David Gibson ,  Young-Gon Kim ,  Craig S. Mitchell ,  Wael Zohni ,  Ilyas Mohammed

Inventor： L. Elliott Pflughaupt ,  David Gibson ,  Young-Gon Kim ,  Craig S. Mitchell ,  Wael Zohni ,  Ilyas Mohammed

IPC: H01L21/31 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/02 ,  H01L23/48 ,  H01L23/485 ,  H01L23/50 ,  H01L23/528 ,  H01L23/66 ,  H01L25/065 ,  H01L31/0336 ,  H05K1/02

CPC classification number: H01L23/528 ,  H01L23/50 ,  H01L23/66 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/78301 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/023 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/00014

Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively connected, as by forming solder bridges, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

Abstract translation: 堆叠式芯片组件包括具有安装在电介质层上的芯片的单独单元和在将芯片的触点与布置在电介质层的周边区域中的端子互连的电介质层上的迹线。 至少一些迹线是将分片选择触点连接到芯片选择端子的多分支迹线。 这些单元彼此堆叠，不同单元的相应端子通过焊球或其它导电元件彼此连接，以形成垂直总线。 在堆叠之前，通过形成焊接桥，各个单元的多分支迹线被选择性地连接，以便在连接到不同的芯片选择端子的不同单元中留下芯片的芯片选择触点，从而将这些芯片连接到不同的垂直总线 。 各个单元期望地是薄的并且直接地彼此邻接，以便提供具有来自堆叠内的芯片的良好热传递的低高度组件。

公开(公告)号：US06969265B2

公开(公告)日：2005-11-29

申请号：US09574647

申请日：2000-05-18

Applicant: Schelto van Doorn

Inventor： Schelto van Doorn

IPC: H01R12/00 ,  H05K1/18

CPC classification number: H05K1/181 ,  H05K2201/10083 ,  H05K2201/1053 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611

Abstract: Apparatus and methods of electrically connecting integrated circuits and transducers are described. In particular, a transducer includes a base mountable on a substrate (e.g., a printed circuit board), and an input/output (I/O) lead configured to contact an I/O lead of an integrated circuit mounted on the substrate. The transducer may be mounted on the substrate to contact the transducer I/O lead to the integrated circuit I/O lead. The transducer I/O lead is configured to electrically connect to the integrated circuit I/O lead independently of any electrically conductive path of the substrate. The direct electrical connection between the transducer and the integrated circuit provides a high-speed communication channel that avoids the parasitic and high-inductance limitations generally associated with conventional metallic printed circuit board traces. At the same time, the transducer is compatible with existing printed circuit board technologies and integrate circuit technologies and, therefore, may be readily integrated into existing computer systems.

Abstract translation: 描述了电连接集成电路和换能器的装置和方法。 特别地，换能器包括可安装在基板（例如印刷电路板）上的基座以及被配置为接触安装在基板上的集成电路的I / O引线的输入/输出（I / O）引线。 传感器可以安装在基板上，以将换能器I / O引导到集成电路I / O引线。 换能器I / O引线被配置为独立于衬底的任何导电路径电连接到集成电路I / O引线。 传感器和集成电路之间的直接电连接提供了高速通信通道，其避免了与常规金属印刷电路板迹线相关的寄生和高电感限制。 同时，传感器与现有的印刷电路板技术兼容，并集成电路技术，因此可以容易地集成到现有的计算机系统中。

公开(公告)号：US06952049B1

公开(公告)日：2005-10-04

申请号：US09538469

申请日：2000-03-29

Applicant: Kouki Ogawa ,  Eiji Kodera

Inventor： Kouki Ogawa ,  Eiji Kodera

IPC: H01G4/232 ,  H01G4/236 ,  H01L23/12 ,  H01L23/13 ,  H01L23/498 ,  H01L23/50 ,  H01L23/64 ,  H01L25/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46 ,  H01L23/053

CPC classification number: H01L23/642 ,  H01G4/232 ,  H01G4/236 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/16268 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/183 ,  H05K3/4602 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/047

Abstract: A capacitor-built-in-type printed wiring substrate which can reliably eliminate noise and attain extremely low resistance and low inductance in connections between an IC chip and the capacitor, and a printed wiring substrate and capacitor for use in the same. A capacitor-built-in-type printed wiring substrate 100 on which an IC chip is mounted includes a capacitor-built-in-type printed wiring substrate 110 and an IC chip 101 mounted on the capacitor-built-in-type printed wiring substrate 110. A printed wiring substrate 120 includes a number of connection-to-IC substrate bumps 152 and a closed-bottomed capacitor accommodation cavity 121 formed therein. A capacitor 130 is disposed in the cavity 121 and includes a pair of electrode groups 133E and 133F and a number of connection-to-IC capacitor bumps 131 connected to either one of the paired electrode groups 133E and 133F. The connection-to-IC capacitor bumps 131 are flip-chip-bonded to corresponding connection-to-capacitor bumps 103 on the IC chip 101. The connection-to-IC substrate bumps 152 are flip-chip-bonded to corresponding connection-to-substrate bumps 104 on the IC chip 101.

Abstract translation: 能够可靠地消除噪声并且在IC芯片和电容器之间的连接中获得极低电阻和低电感的电容器内置型印刷布线基板，以及用于其中的印刷布线基板和电容器。 其上安装有IC芯片的电容器内置型印刷布线基板100包括电容器内置式印刷布线基板110和安装在电容器内置型印刷布线基板上的IC芯片101 110。 印刷布线基板120包括多个连接到IC的基板凸块152和形成在其中的封闭的电容器容纳腔121。 电容器130设置在空腔121中，并且包括一对电极组133E和133F以及连接到一对电极组133E和133F中的任一个的多个连接到IC电容器凸块131.连接 IC电容器凸块131与IC芯片101上的对应连接电容器凸块103倒装芯片接合。 连接IC基板凸块152与IC芯片101上的对应连接对基板凸块104倒装芯片接合。

公开(公告)号：US06950300B2

公开(公告)日：2005-09-27

申请号：US10694306

申请日：2003-10-27

Applicant: Sehat Sutardja

Inventor： Sehat Sutardja

IPC: H01G4/12 ,  H01G4/232 ,  H01G4/252 ,  H01G4/30 ,  H01G4/40 ,  H02M3/155 ,  H05K1/02 ,  H01G4/228 ,  H01G4/06

CPC classification number: H01G4/232 ,  H01G4/30 ,  H01G4/35 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/0233 ,  H05K2201/10515 ,  H05K2201/1053

Abstract: A multilayer capacitor having a low parasitic inductance includes a first electrode, a second electrode, a dielectric, a first contact, and a second contact. The first electrode is substantially rectangular and it includes a first contact finger. The dielectric has a first surface and a second surface, wherein the first and second surfaces are situated opposite with each other. The first surface of the dielectric is coupled with the first electrode. The second electrode is substantially rectangular and it includes a first contact finger. The second electrode is coupled to the second surface of the dielectric. The first contact is coupled to the first contact finger of the first electrode. The second contact is coupled to the first contact finger of the second electrode. The second contact is situated at a minimal space from the first contact to reduce the parasitic inductance.

Abstract translation: 具有低寄生电感的层叠电容器包括第一电极，第二电极，电介质，第一接触和第二接触。 第一电极基本上是矩形的，它包括第一接触指。 电介质具有第一表面和第二表面，其中第一表面和第二表面彼此相对设置。 电介质的第一表面与第一电极耦合。 第二电极基本上是矩形的，它包括第一接触指。 第二电极耦合到电介质的第二表面。 第一触点耦合到第一电极的第一接触指。 第二触点耦合到第二电极的第一接触指。 第二触点位于与第一触点最小的空间上，以减小寄生电感。

公开(公告)号：US20040183193A1

公开(公告)日：2004-09-23

申请号：US10803879

申请日：2004-03-19

Applicant: FUJITSU LIMITED

Inventor： Masateru Koide ,  Misao Umematsu ,  Takashi Kanda ,  Yasuhiro Usui ,  Kenji Fukuzono

IPC: H01L023/34

CPC classification number: H01L23/642 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/4006 ,  H01L23/49833 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/19106 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/141 ,  H05K1/182 ,  H05K3/3436 ,  H05K2201/049 ,  H05K2201/09072 ,  H05K2201/1053 ,  H05K2201/10734 ,  H05K2201/10977 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A packaging method, a packaging structure and a package is substrate capable of restraining a warp of a thin film substrate, increasing a product yield, and building up a sufficient cooling capacity in the case of mounting an LSI having a high exothermic quantity. A package substrate 1 of the invention is such that an opening 11 is formed in a first substrate 12, a thin film substrate (a second substrate) 13 is laminated on the first substrate 12, the opening 11 is covered with the thin film substrate 13. Next, a capacitor (a first electronic part) 14 is inserted into the opening 11 and bonded to the thin film substrate, a resin 15 fills an interior of the opening 11 to a fixed or larger thickness and is hardened, the thin film substrate 13 and the capacitor 14 are thereby sustained by the resin 15, an LSI 16 (a second electronic part) that should be connected to the capacitor 14 is bonded to a surface, on an exposed side, of the thin film substrate 13, and the capacitor 14 is connected to the LSI 16.

Abstract translation: 包装方法，包装结构和包装是能够抑制薄膜基板翘曲的基板，提高产品收率，并且在安装具有高放热量的LSI的情况下建立足够的冷却能力的基板。 本发明的封装基板1使得在第一基板12中形成开口11，在第一基板12上层叠薄膜基板（第二基板）13，开口11被薄膜基板13覆盖 接下来，将电容器（第一电子部件）14插入到开口11中并且结合到薄膜基板上，树脂15将开口11的内部填充到固定或更大的厚度并被硬化，薄膜基板 13并且电容器14由树脂15维持，应该连接到电容器14的LSI 16（第二电子部件）被接合到薄膜基板13的暴露侧的表面上，并且 电容器14连接到LSI 16。

公开(公告)号：US20040175966A1

公开(公告)日：2004-09-09

申请号：US10379844

申请日：2003-03-04

Inventor： William O. Alger ,  Gary B. Long ,  Gary A. Brist ,  Carlos Mejia

IPC: H01R012/00

CPC classification number: H05K1/0263 ,  H05K1/141 ,  H05K1/147 ,  H05K7/1092 ,  H05K2201/10189 ,  H05K2201/1053 ,  H05K2201/10704

Abstract: An apparatus for receiving a microchip and having a conductor buses therein. A top surface of the apparatus receives the microchip while the bottom surface is to mount to a circuit board. A plurality of pin receptacles pass through the top surface to receive a corresponding plurality of microchip pins of the microchip. The conductor bus resides at least in part between the top surface and the bottom surface and is electrically coupled to a first plurality of the plurality of the pin receptacles.

Abstract translation: 一种用于接收微芯片并在其中具有导体总线的装置。 该装置的顶表面接收微芯片，同时底表面将安装到电路板上。 多个销插座通过顶表面以接收微芯片的对应的多个微芯片引脚。 导体总线至少部分地位于顶表面和底表面之间，并且电耦合到第一多个多个销插座。