公开(公告)号：US08272124B2

公开(公告)日：2012-09-25

申请号：US12418438

申请日：2009-04-03

Applicant: Treliant Fang ,  Michael Harburn ,  Onnik Yaglioglu

Inventor： Treliant Fang ,  Michael Harburn ,  Onnik Yaglioglu

IPC: B81C1/00 ,  H01R13/02

CPC classification number: G01R3/00 ,  B81C1/00031 ,  G01R1/0483 ,  G01R1/06744 ,  G01R1/07314 ,  H05K3/4007 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/0367 ,  H05K2201/10977 ,  H05K2203/0338 ,  Y10T29/49147 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/4921 ,  Y10T29/49222 ,  Y10T428/24174

Abstract: A technique for anchoring carbon nanotube columns to a substrate can include use of a filler material placed onto the surface of the substrate into area between the columns and surrounding a base portion of each of the columns.

Abstract translation: 用于将碳纳米管柱锚定到基底的技术可以包括使用放置在基底表面上的填充材料到列之间的区域并围绕每个柱的基部。

公开(公告)号：US20120183775A1

公开(公告)日：2012-07-19

申请号：US13498161

申请日：2010-10-08

Applicant: Yoichi Shinba ,  Shoichi Niizeki ,  Toshihisa Nonaka

Inventor： Yoichi Shinba ,  Shoichi Niizeki ,  Toshihisa Nonaka

IPC: H05K3/22 ,  C09K5/00 ,  B32B15/02 ,  C23C22/06 ,  C23C22/07

CPC classification number: C09C3/10 ,  C01P2004/03 ,  C01P2004/62 ,  C01P2004/84 ,  C01P2006/40 ,  C09C1/62 ,  C09C1/64 ,  C09C1/644 ,  H05K3/28 ,  H05K2201/0224 ,  H05K2201/10977 ,  H05K2203/122 ,  Y10T428/2991

Abstract: Disclosed is a process which comprises bringing an acidic organic substance or phosphoric acid into contact with a metal to form, on the surface of the metal, a layer that contains either an organic acid salt formed from both the acidic organic substance and the metal or a phosphoric acid salt formed from both the phosphoric acid and the metal. In the process, the layer can be selectively formed only on the surface of the metal. When the process is applied to the production of core-shell particles, neither agglomeration of the particles nor viscosity increase of the fluid occurs, while when the process is applied to the production of a covered metal-wiring circuit board, the layer can be selectively formed only in the metal area to be covered.

Abstract translation: 公开了一种方法，其包括使酸性有机物质或磷酸与金属接触以在金属表面上形成含有由酸性有机物质和金属形成的有机酸盐的层或 由磷酸和金属形成的磷酸盐。 在该过程中，该层可以仅选择性地形成在金属的表面上。 当将该方法应用于核 - 壳颗粒的生产时，不会发生颗粒的聚集或流体的粘度增加，而当该方法应用于覆盖金属布线电路板的生产时，该层可以是选择性的 仅在被覆盖的金属区域形成。

公开(公告)号：US08208270B2

公开(公告)日：2012-06-26

申请号：US12280434

申请日：2007-04-23

Applicant: Masato Mori ,  Daido Komyoji ,  Koichi Nagai ,  Yoshihiko Yagi

Inventor： Masato Mori ,  Daido Komyoji ,  Koichi Nagai ,  Yoshihiko Yagi

IPC: H05K1/11

CPC classification number: H05K1/144 ,  B23K1/0016 ,  B23K2101/42 ,  H05K3/368 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2201/2018 ,  H05K2203/1572

Abstract: Three-dimensional structure (40) of the present invention includes first module board (28), second module board (37), and substrate joining member (10) that unifies board (28) and board (37) into one body, thereby electrically connecting these two elements together. The unification is done by molding the outer wall of housing (12) of substrate joining member (10) with resin (29). Substrate joining member (10) used in the three-dimensional structure (40) includes multiple lead terminals (14) made of conductive material, and a frame-shaped and insulating housing (12) to which frame the lead terminals (14) are fixed vertically in a predetermined array. Housing (12) includes projections (18) on at least two outer wall faces of its frame shape.

Abstract translation: 本发明的三维结构（40）包括将板（28）和板（37）一体化成一体的第一模块板（28），第二模块板（37）和基板接合构件（10），由此电 将这两个元素连接在一起。 通过用树脂（29）将衬底接合构件（10）的壳体（12）的外壁模制成一体。 在三维结构（40）中使用的基板接合构件（10）包括由导电材料制成的多个引线端子（14）和框架形绝缘壳体（12），引线端子（14）固定到框架形绝缘壳体 垂直于预定的阵列。 壳体（12）在其框架形状的至少两个外壁面上包括突起（18）。

公开(公告)号：US08183090B2

公开(公告)日：2012-05-22

申请号：US12856168

申请日：2010-08-13

Applicant: Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

Inventor： Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

IPC: H05K3/10

CPC classification number: H05K3/305 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/0262 ,  H05K1/056 ,  H05K1/141 ,  H05K1/183 ,  H05K3/107 ,  H05K3/4614 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09972 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0278 ,  H05K2203/1189 ,  Y02P70/613 ,  Y10T29/49155

Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer. The first and second conductive parts form connecting areas in the insulating layer, thereby connecting the first and second circuit substrates electrically.

Abstract translation: 为了减少设置在芯基板上的电路基板与要安装在其上的电路之间的连接缺陷，从而提高作为多层器件安装基板的可靠性。 装置安装基板包括：由基板，形成在该基板上的绝缘层和形成在该绝缘层上的第一导电层（包括导电部分）构成的第一电路基板; 以及安装在第一电路基板上的第二电路基板，由基底，形成在基底的底部上的第二导电层（包括导电部）和形成在基底的顶部的第三导电层 的基地。 这里，第一和第二电路基板通过压力接合，使得第一和第二导电部件层叠并嵌入到绝缘层中。 第一和第二导电部分形成绝缘层中的连接区域，从而电连接第一和第二电路基板。

公开(公告)号：US20120103673A1

公开(公告)日：2012-05-03

申请号：US13346087

申请日：2012-01-09

Applicant: Nobuaki HASHIMOTO

Inventor： Nobuaki HASHIMOTO

IPC: H05K1/02

CPC classification number: H05K3/325 ,  G02F2001/13456 ,  H01L2224/05001 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13008 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/305 ,  H05K2201/0314 ,  H05K2201/10128 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2224/05099

Abstract: A mounting structure of an electronic component includes: a bump electrode included in the electronic component, the bump electrode having an internal resin as a core and a conductive film covering a surface of the internal resin, and elastically deforming so as to follow a shape of at least one corner of a terminal so that the conductive film makes direct conductive contact with at least part of a top surface of the terminal and at least part of a surface along a thickness direction of the terminal; a substrate having the terminal and the electronic component that is mounted on the substrate; and a holding unit provided to the substrate and the electronic component so as to hold a state in which the bump electrode electrically deformed makes conductive contact with the terminal.

Abstract translation: 电子部件的安装结构包括：包括在电子部件中的凸块电极，具有内部树脂作为芯的凸块电极和覆盖内部树脂的表面的导电膜，并且弹性变形，以便遵循 端子的至少一个角部，使得导电膜与端子的顶表面的至少一部分和沿着端子的厚度方向的表面的至少一部分直接导电接触; 具有安装在基板上的端子和电子部件的基板; 以及保持单元，其设置到所述基板和所述电子部件，以保持所述凸起电极变形的状态与所述端子导电接触。

公开(公告)号：US08154122B2

公开(公告)日：2012-04-10

申请号：US12469253

申请日：2009-05-20

Applicant: Chul-Yong Jang ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

Inventor： Chul-Yong Jang ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L21/4846 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H05K3/3436 ,  H05K2201/10977 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor package and a method of manufacturing the semiconductor package are provided. A semiconductor package according to the present general inventive concept may include a base substrate having one surface on which a connection terminal is formed and a first package substrate having a molding layer covering the base substrate. The molding layer faces a circumference of the connection terminal and includes a side surface having first and second surfaces having a circumference of a different size, respectively.

Abstract translation: 提供半导体封装和制造半导体封装的方法。 根据本发明总体构思的半导体封装可以包括其上形成有连接端子的一个表面的基底基板和具有覆盖基底基板的成型层的第一封装基板。 模制层面向连接端子的圆周，并且包括分别具有不同尺寸的圆周的第一表面和第二表面的侧表面。

公开(公告)号：US08143531B2

公开(公告)日：2012-03-27

申请号：US12276772

申请日：2008-11-24

Applicant: Syota Miki ,  Tadashi Arai

Inventor： Syota Miki ,  Tadashi Arai

IPC: H05K1/16

CPC classification number: H05K3/284 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K3/3436 ,  H05K2201/0989 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2201/10977 ,  H01L2924/00

Abstract: An electronic component mounting package includes a structure (coreless substrate) in which a plurality of wiring layers are stacked one on top of another with insulating layers interposed therebetween and are interconnected through via holes formed in the insulating layers. The entire surface of the coreless substrate, exclusive of pad portions defined at desired positions of the outermost wiring layers thereof, is covered with a molding resin. Further, an interposer is mounted on the side of the electronic component mounting surface of the coreless substrate, and the molding resin is partially filled into a gap between the coreless substrate and the interposer.

Abstract translation: 电子部件安装封装包括其中多个布线层一层叠置在其上的绝缘层并且通过形成在绝缘层中的通孔相互连接的结构（无芯基板）。 无芯基板的整个表面，不包括限定在其最外面布线层的期望位置的焊盘部分，被模制树脂覆盖。 此外，在无芯基板的电子部件安装面的一侧安装有插入体，将成型树脂部分地填充到无芯基板和插入件之间的间隙中。

公开(公告)号：US08124881B2

公开(公告)日：2012-02-28

申请号：US12394889

申请日：2009-02-27

Applicant: Noriyuki Shirasawa

Inventor： Noriyuki Shirasawa

IPC: H05K1/16 ,  H05K7/00 ,  H01L23/48

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/13 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H05K3/3452 ,  H05K2201/09063 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49121 ,  Y10T29/49126 ,  H01L2924/00

Abstract: A printed board comprising a packaging surface on which an electronic component is packaged, an adhesion prohibited portion which is provided at a region of the printed board different from a region where the electronic component is provided, and to which adhesion of the adhesive material is prohibited, and a blocking step portion which is formed at a region between the region where the electronic component is provided and the region where the adhesion prohibited portion is provided, which blocks any adhesive material which has spilled out from between the bottom surface of the electronic component and the packaging surface from reaching the adhesion prohibited portion.

Abstract translation: 一种印刷电路板，包括封装有电子部件的封装表面，设置在与设置有电子部件的区域不同的印刷电路板的区域的粘合禁止部分，并且粘合剂材料的粘合被禁止 以及阻挡台阶部，其形成在设置有电子部件的区域与设置有防粘连部的区域之间的区域，该阻挡台阶部阻挡从电子部件的底面之间溅出的任何粘接材料 并且包装表面到达不粘附部分。

公开(公告)号：US20120002386A1

公开(公告)日：2012-01-05

申请号：US12828907

申请日：2010-07-01

Applicant: Lasse Juhani Pykari ,  David L. Lu

Inventor： Lasse Juhani Pykari ,  David L. Lu

IPC: H05K7/00 ,  H05K3/34

CPC classification number: H05K3/3489 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K2201/10977 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: In accordance with an example embodiment of the present invention, a method, comprises receiving an integrated circuit component comprising at least one solder ball substantially surrounded by a first epoxy flux, applying a second epoxy flux to at least one integrated circuit component contact point of a printed circuit board, and performing a reflow process such that the integrated circuit component adheres to the printed circuit board and the first and second epoxy flux forms an encapsulating layer around at least one solder joint.

Abstract translation: 根据本发明的示例性实施例，一种方法包括接收集成电路部件，该集成电路部件包括基本上由第一环氧树脂焊剂包围的至少一个焊球，将第二环氧树脂焊剂施加至至少一个集成电路部件接触点 印刷电路板，并且执行回流处理，使得集成电路部件粘附到印刷电路板，并且第一和第二环氧树脂焊剂在至少一个焊点周围形成封装层。

公开(公告)号：US08071433B2

公开(公告)日：2011-12-06

申请号：US12868422

申请日：2010-08-25

Applicant: Erich Syri ,  Gerold Gruendler ,  Juergen Hoegerl ,  Thomas Killer ,  Volker Strutz

Inventor： Erich Syri ,  Gerold Gruendler ,  Juergen Hoegerl ,  Thomas Killer ,  Volker Strutz

IPC: H01L21/00 ,  H01L21/337

CPC classification number: H01L25/165 ,  H01L21/563 ,  H01L23/293 ,  H01L2224/73203 ,  H05K1/181 ,  H05K3/305 ,  H05K2201/10045 ,  H05K2201/10977 ,  Y02P70/613

Abstract: A semiconductor component including: a substrate, at least one semiconductor chip arranged on the substrate and at least one passive device likewise arranged on the substrate. The passive device is mounted with its underside on the substrate. The semiconductor component further includes an interspace disposed between the underside of the passive device and the substrate. The interspace is filled with an underfilling material. In order to avoid the solder pumping effect, the upper side and the lateral sides of the passive device are also embedded in a plastic compound.

Abstract translation: 一种半导体部件，包括：衬底，布置在衬底上的至少一个半导体芯片和同样布置在衬底上的至少一个无源器件。 无源器件的底面安装在基板上。 半导体部件还包括设置在无源器件的下侧和衬底之间的间隙。 该间隙填充有底部填充材料。 为了避免焊料泵送效应，无源器件的上侧和侧面也嵌入塑料化合物中。