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    Safety features for high level design
    82.
    发明授权
    Safety features for high level design 有权

    公开(公告)号：US10007748B2

    公开(公告)日：2018-06-26

    申请号：US15633461

    申请日：2017-06-26

    Applicant: ALTERA CORPORATION

    Inventor： Adam Titley

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F17/5045 ,  G06F17/5054

    Abstract: This disclosure relates generally to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. Compiling the algorithmic description may involve identifying the at least one construct, accessing a first safety data type definition associated with the first safety data type, and generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition. The second representation can be provided in a second language and include at least one safety feature for a portion of the circuit design associated with the at least one construct.

    Programmable integrated circuits with in-operation reconfiguration capability
    84.
    发明授权
    Programmable integrated circuits with in-operation reconfiguration capability 有权

    公开(公告)号：US09984734B2

    公开(公告)日：2018-05-29

    申请号：US15471325

    申请日：2017-03-28

    Applicant: Altera Corporation

    Inventor： Andy L. Lee ,  Shankar Sinha ,  Ning Cheng

    IPC: G11C7/00 ,  G11C7/22 ,  G11C5/14 ,  G11C7/20

    CPC classification number: G11C7/22 ,  G11C5/14 ,  G11C7/20 ,  G11C11/413 ,  G11C11/419 ,  G11C2207/002

    Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

    Pipelined systolic finite impulse response filter
    85.
    发明授权
    Pipelined systolic finite impulse response filter 有权

    公开(公告)号：US09966933B1

    公开(公告)日：2018-05-08

    申请号：US15161210

    申请日：2016-05-21

    Applicant: Altera Corporation

    Inventor： Volker Mauer ,  Martin Langhammer

    IPC: G06F17/10 ,  H03H17/02

    CPC classification number: H03H17/0248 ,  H03H17/06 ,  H03H2220/04 ,  H03H2220/06

    Abstract: A systolic FIR filter circuit includes a plurality of multipliers, a plurality of sample pre-adders, each respective one of the sample pre-adders connected to a sample input of a respective multiplier, and an output cascade adder chain including a respective output adder connected to a respective multiplier. The output cascade adder chain includes a selectable number of delays between adjacent output adders. An input sample chain has a first leg and a second leg. Each respective one of the sample pre-adders receives a respective input from the first leg and a respective input from the second leg. The input sample chain has, between adjacent sample points in at least one of the legs, a selectable number of sample delays related to the selectable number of output delays. Connections of inputs from the input sample chain to the sample pre-adders are adjusted to account for the selectable number.

    High-speed serial data signal receiver circuitry
    87.
    发明授权
    High-speed serial data signal receiver circuitry 有权

    公开(公告)号：US09960937B2

    公开(公告)日：2018-05-01

    申请号：US15495622

    申请日：2017-04-24

    Applicant: Altera Corporation

    Inventor： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Y. Shumarayev

    IPC: H04L25/03 ,  H04L7/00

    CPC classification number: H04L25/03885 ,  H04L7/0054 ,  H04L25/03019 ,  H04L25/03878

    Abstract: Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

    Circuit design implementations in secure partitions of an integrated circuit
    88.
    发明授权
    Circuit design implementations in secure partitions of an integrated circuit 有权

    公开(公告)号：US09946826B1

    公开(公告)日：2018-04-17

    申请号：US14843313

    申请日：2015-09-02

    Applicant: Altera Corporation

    Inventor： Sean Atsatt ,  Ting Lu ,  Dana How ,  Herman Schmit

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F17/5054

    Abstract: In server virtualization, the resources of an integrated circuit are partitioned into smaller portions, and each of these smaller portions is then operated independently. Software is used to represent the smaller portions as virtual environments. For the purpose of server virtualization, an integrated circuit may include several different circuit designs, each implemented in a secure partition in the integrated circuit. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be verified as un-altered and from the respective user or owner and as having been approved by the integrated circuit owner and/or the circuit design implementation owner. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be operated securely and independently of the other circuit design implementations in the integrated circuit.

    Phase-locked loops with electrical overstress protection circuitry
    90.
    发明授权
    Phase-locked loops with electrical overstress protection circuitry 有权

    公开(公告)号：US09941890B2

    公开(公告)日：2018-04-10

    申请号：US15187534

    申请日：2016-06-20

    Applicant: Altera Corporation

    Inventor： Chee Seng Leong

    IPC: H03L7/06 ,  H03L7/08 ,  H03L7/099 ,  H03L7/089 ,  H03L7/091

    CPC classification number: H03L7/0807 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/0995 ,  H03L7/14

    Abstract: An integrated circuit with a phase-locked loop (PLL) is provided. The PLL may include a phase frequency detector, a charge pump, a source follower circuit, a variable oscillator, a frequency divider, and a control block. The phase frequency detector may be configured to align or lock a feedback clock signal to a reference clock signal. The control block includes clock loss detection circuits that are used to determine whether the reference clock signal or the feedback clock signal has stopped toggling. In response to detecting a clock loss event for either the reference or the feedback clock signal, the control block may disable the phase frequency detector to place the charge pump in a tristate mode and may apply a predetermined bias voltage to the source follower circuit to help minimize electrical overstress.

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