公开(公告)号：US20100203739A1

公开(公告)日：2010-08-12

申请号：US12452692

申请日：2008-07-02

Applicant: Volker Becker ,  Franz Laermer ,  Tino Fuchs ,  Christina Leinenbach

Inventor： Volker Becker ,  Franz Laermer ,  Tino Fuchs ,  Christina Leinenbach

IPC: H01L21/306 ,  C23F1/08

CPC classification number: H01L21/3065 ,  B81C1/00531 ,  B81C1/00595 ,  B81C2201/0132 ,  B81C2201/0138 ,  H01L21/02019 ,  H01L21/30621 ,  H01L21/32135

Abstract: A method for selective etching of an SiGe mixed semiconductor layer on a silicon semiconductor substrate by dry chemical etching of the SiGe mixed semiconductor layer with the aid of an etching gas selected from the group including ClF3 and/or ClF5, a gas selected from the group including Cl2 and/or HCl being added to the etching gas.

Abstract translation: 借助于选自ClF3和/或ClF5的蚀刻气体，通过SiGe混合半导体层的干法化学蚀刻来选择性地蚀刻硅半导体衬底上的SiGe混合半导体层的方法， 包括添加到蚀刻气体中的Cl 2和/或HCl。

公开(公告)号：US07772024B2

公开(公告)日：2010-08-10

申请号：US10554642

申请日：2004-04-26

Applicant: Robert Van Kampen ,  Charles Gordon Smith ,  Jack Luo ,  Andrew John Weeks

Inventor： Robert Van Kampen ,  Charles Gordon Smith ,  Jack Luo ,  Andrew John Weeks

IPC: H01L21/00

CPC classification number: B81C1/0015 ,  B81C2201/0109 ,  B81C2201/0132 ,  H01H59/0009

Abstract: A method of manufacturing a micromechanical element wherein the method comprises the steps of providing a layer of base material, applying at least one at least partly sacrificial layer of an etchable material, patterning the at least partly sacrificial layer, to define at least a portion of the shape of the element, applying at least one structural layer of a mechanical material, patterning the structural layer to form at least a portion of the element, and removing at least partly the patterned at least partly sacrificial layer to release partly free the element. The mechanical material is selected from the group of conductive materials.

Abstract translation: 一种制造微机械元件的方法，其中所述方法包括以下步骤：提供基材层，施加可蚀刻材料的至少一个至少部分牺牲层，图案化所述至少部分牺牲层，以限定至少部分牺牲层 元件的形状，施加机械材料的至少一个结构层，图案化结构层以形成元件的至少一部分，以及至少部分去除图案化的至少部分牺牲层以释放部分地释放元件。 机械材料选自导电材料组。

公开(公告)号：US20100193781A1

公开(公告)日：2010-08-05

申请号：US12514304

申请日：2007-11-09

Applicant: Sudhiranjan Tripathy ,  Vicknesh s/o Sahmuganathan

Inventor： Sudhiranjan Tripathy ,  Vicknesh s/o Sahmuganathan

IPC: H01L29/22 ,  H01L29/20 ,  H01L29/16 ,  H01L21/203

CPC classification number: B81C1/00484 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2201/017

Abstract: A micromechanical structure and a method of fabricating a micromechanical structure are provided. The micromechanical structure comprises a silicon (Si) based substrate; a micromechanical element formed directly on the substrate; and an undercut formed underneath a released portion of the micromechanical element; wherein the undercut is in the form of a recess formed in the Si based substrate.

Abstract translation: 提供微机械结构和制造微机械结构的方法。 微机械结构包括基于硅（Si）的衬底; 直接形成在基板上的微机械元件; 以及形成在微机械元件的释放部分下方的底切; 其中所述底切为形成在所述Si基衬底中的凹部的形式。

公开(公告)号：US07760435B2

公开(公告)日：2010-07-20

申请号：US11816804

申请日：2005-02-21

Applicant: Massimo Tormen ,  Alessandro Carpentiero ,  Enzo Mario Di Fabrizio

Inventor： Massimo Tormen ,  Alessandro Carpentiero ,  Enzo Mario Di Fabrizio

IPC: G02B27/10 ,  B29D11/00 ,  C03C15/00

CPC classification number: B81C99/009 ,  B81B2207/056 ,  B81C99/0085 ,  B81C2201/0132 ,  B81C2201/0143 ,  B82Y20/00 ,  G02B3/0012

Abstract: A method is for forming three-dimensional micro- and nanostructures, based on the structuring of a body of material by a mould having an impression area which reproduces the three-dimensional structure in negative form. This method includes providing a mould having a substrate of a material which can undergo isotropic chemical etching, in which the impression area is to be formed. An etching pattern is defined on (in) the substrate, having etching areas having zero-, uni- or bidimensional extension, which can be reached by an etching agent. A process of isotropic chemical etching of the substrate from the etching areas is carried out for a corresponding predetermined time, so as to produce cavities which in combination make up the impression area. The method is advantageously used in the fabrication of sets of microlenses with a convex three-dimensional structure, of the refractive or hybrid refractive/diffractive type, for forming images on different focal planes.

Abstract translation: 一种用于形成三维微结构和纳米结构的方法，其基于通过具有以负形式再现三维结构的印模区域的模具构造材料体。 该方法包括提供具有能够进行各向同性化学蚀刻的材料的基材的模具，其中将形成印模区域。 蚀刻图案被定义在衬底的（在）中，其蚀刻区域具有零，一维或二维延伸，这可由蚀刻剂达到。 从蚀刻区域对基板进行各向同性化学蚀刻的过程进行相应的预定时间，以产生组合构成印模区域的空腔。 该方法有利地用于制造具有折射或混合折射/衍射类型的凸立体结构的微透镜组，用于在不同焦平面上形成图像。

公开(公告)号：US20090301999A1

公开(公告)日：2009-12-10

申请号：US12542659

申请日：2009-08-17

Applicant: Darrell LaRue McReynolds ,  Kia Silverbrook

Inventor： Darrell LaRue McReynolds ,  Kia Silverbrook

IPC: G11B5/127

CPC classification number: H01L21/02057 ,  B41J2/1412 ,  B41J2/1601 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/164 ,  B81B2201/052 ,  B81B2203/033 ,  B81C1/00849 ,  B81C2201/0112 ,  B81C2201/0132

Abstract: A method of forming an ink supply channel for an inkjet printhead comprises the steps of: (i) providing a wafer having a frontside and a backside; (ii) etching a plurality of frontside trenches into the frontside; (iii) filling each of the trenches with a photoresist plug; (iv) forming nozzle structures on the frontside using MEMS fabrication processes; (v) etching a backside trench from the backside, the backside trench meeting with one or more of the plugs; (vi) removing a portion of each photoresist plug via the backside trench by subjecting the backside to a biased oxygen plasma etch, thereby exposing sidewall features in the backside trench; (vii) modifying the exposed sidewall features; and (viii) removing the photoresist plugs to form the ink supply channel. The ink supply channel connects the backside to the frontside.

Abstract translation: 一种形成用于喷墨打印头的供墨通道的方法包括以下步骤：（i）提供具有前侧和后侧的晶片; （ii）将多个前侧沟槽蚀刻到前侧; （iii）用光致抗蚀剂插塞填充每个沟槽; （iv）使用MEMS制造工艺在前侧形成喷嘴结构; （v）从背面蚀刻背面沟槽，所述背面沟槽与一个或多个所述插头相会合; （vi）通过使背面经受偏压的氧等离子体蚀刻，从而暴露背面沟槽中的侧壁特征，通过背侧沟槽去除每个光致抗蚀剂插塞的一部分; （vii）修改暴露的侧壁特征; 和（viii）去除光致抗蚀剂插头以形成供墨通道。 供墨通道将背面连接到前侧。

公开(公告)号：US07588693B2

公开(公告)日：2009-09-15

申请号：US11242916

申请日：2005-10-05

Applicant: Darrell LaRue McReynolds ,  Kia Silverbrook

Inventor： Darrell LaRue McReynolds ,  Kia Silverbrook

IPC: C23F1/00 ,  G01D15/00

CPC classification number: H01L21/02057 ,  B41J2/1412 ,  B41J2/1601 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/164 ,  B81B2201/052 ,  B81B2203/033 ,  B81C1/00849 ,  B81C2201/0112 ,  B81C2201/0132

Abstract: A process for facilitating modification of an etched trench is provided. The process comprises: (a) providing a wafer comprising an etched trench, the trench having a photoresist plug at its base; and (b) removing a portion of the photoresist by subjecting the wafer to a biased oxygen plasma etch. The process is particularly suitable for preparing a trench for subsequent argon ion milling. Printhead integrated circuits fabricated by a process according to the invention have improved ink channel surface profiles and/or surface properties.

Abstract translation: 提供了一种便于修改蚀刻沟槽的工艺。 该方法包括：（a）提供包括蚀刻沟槽的晶片，所述沟槽在其底部具有光致抗蚀剂插塞; 和（b）通过对晶片进行偏压氧等离子体蚀刻来去除一部分光致抗蚀剂。 该方法特别适用于制备后续氩离子研磨的沟槽。 通过根据本发明的方法制造的印刷头集成电路具有改进的油墨通道表面轮廓和/或表面性质。

公开(公告)号：US20090090693A1

公开(公告)日：2009-04-09

申请号：US11944247

申请日：2007-11-21

Applicant: Chuanwei WANG

Inventor： Chuanwei WANG

IPC: B44C1/22

CPC classification number: B81C1/00246 ,  B81C2201/0132 ,  B81C2203/0714 ,  B81C2203/0742

Abstract: A method for fabricating micromachined structures is provided. At least one cavity is formed on a substrate and then a dielectric material different from the material of the substrate is filled in the at least one cavity. Next, a circuitry layer including a first etch-resistant layer and a dielectric layer is formed above the at least one cavity filled with the dielectric material. A portion of the circuitry layer exposed by the first etch-resistant layer is then etched. Finally, the dielectric material in the at least one cavity is etched out.

Abstract translation: 提供了一种制造微加工结构的方法。 在衬底上形成至少一个空腔，然后将不同于衬底的材料的电介质材料填充在至少一个空腔中。 接下来，在填充有电介质材料的至少一个空腔的上方形成包括第一耐蚀刻层和电介质层的电路层。 然后蚀刻由第一耐蚀刻层暴露的电路层的一部分。 最后，蚀刻出至少一个空腔中的介电材料。

公开(公告)号：US20090011158A1

公开(公告)日：2009-01-08

申请号：US12050209

申请日：2008-03-18

Applicant: YEHOSHUA YESHURUN

Inventor： YEHOSHUA YESHURUN

IPC: B29D22/00 ,  H01L21/00

CPC classification number: B81C1/00111 ,  A61M37/0015 ,  A61M2037/003 ,  A61M2037/0053 ,  B81B2201/055 ,  B81C2201/0132 ,  B81C2201/0133 ,  Y10T428/13

Abstract: A method for forming a hollow microneedle structure includes processing the front side of a wafer to form at least one microneedle projecting from a substrate with a first part of a through-bore, formed by a dry etching process, passing through the microneedle and through a part of a thickness of the substrate. The backside of the wafer is also processed to form a second part of the through-bore by a wet etching process.

Abstract translation: 一种用于形成中空微针结构的方法包括处理晶片的前侧，以形成至少一个从基底突出的微针，该微针具有通过干蚀刻工艺形成的通孔的第一部分，穿过微针并通过 基板厚度的一部分。 晶片的背面也被处理以通过湿蚀刻工艺形成通孔的第二部分。

公开(公告)号：US07419917B2

公开(公告)日：2008-09-02

申请号：US11504466

申请日：2006-08-15

Applicant: Margaret H. Abraham

Inventor： Margaret H. Abraham

IPC: H01L21/31

CPC classification number: H01L21/31116 ,  B81C1/00484 ,  B81C2201/0132 ,  B81C2201/0143 ,  H01L21/26533

Abstract: A method is used for producing nanoscale and microscale devices in a variety of materials, such as silicon dioxide patterned buried films. The method is inexpensive and reliable for making small scale mechanical, optical, or electrical devices and relies upon the implantation of ions into a substrate and subsequent annealing to form a stoichiometric film with the device geometry is defined by the implant energy and dose and so is not limited by the usual process parameters.

Abstract translation: 一种方法用于生产各种材料中的纳米级和微量元件，例如二氧化硅图案化的掩膜。 该方法对于制造小规模机械，光学或电气装置而言是便宜且可靠的，并且依赖于将离子注入衬底并随后退火以形成化学计量膜，其中器件几何形状由注入能量和剂量限定，因此 不受通常工艺参数的限制。

公开(公告)号：US07368396B2

公开(公告)日：2008-05-06

申请号：US11173395

申请日：2005-07-01

Applicant: James M. Mrvos ,  Girish S. Patil ,  Karthik Vaideeswaran

Inventor： James M. Mrvos ,  Girish S. Patil ,  Karthik Vaideeswaran

IPC: H01L21/302 ,  H01L21/461

CPC classification number: B81C1/00531 ,  B81C2201/0132 ,  H01J37/321 ,  H01L21/30655 ,  H01L21/3081

Abstract: A process for etching semiconductor substrates using a deep reactive ion etching process to produce through holes or slots (referred to collectively as “slots”) in the substrates. The process includes applying a first layer to a first surface of substrate to provide an etch mask material layer on the first surface of the substrate. A second layer is applied to a second surface of the substrate to provide an etch stop material layer on the second surface of the substrate. The first layer and the second layer have similar solubilities in one or more organic solvents. The substrate is etched from the first surface of the wafers to provide a slot in the substrate. After etching the substrate, the etch mask material layer and the etch stop material layer are removed by contacting the first surface and the second surface of the substrate with a single organic solvent.

Abstract translation: 使用深反应离子蚀刻工艺蚀刻半导体衬底以在衬底中产生通孔或槽（统称为“槽”）的工艺。 该方法包括将第一层施加到衬底的第一表面以在衬底的第一表面上提供蚀刻掩模材料层。 将第二层施加到衬底的第二表面，以在衬底的第二表面上提供蚀刻停止材料层。 第一层和第二层在一种或多种有机溶剂中具有类似的溶解度。 从晶片的第一表面蚀刻衬底以在衬底中提供槽。 在蚀刻基板之后，通过用单一有机溶剂接触基板的第一表面和第二表面来去除蚀刻掩模材料层和蚀刻停止材料层。