公开(公告)号：US20090083976A1

公开(公告)日：2009-04-02

申请号：US12010197

申请日：2008-01-22

Applicant: Jong-Jin Lee

Inventor： Jong-Jin Lee

IPC: H05K3/00

CPC classification number: H05K3/423 ,  H05K1/116 ,  H05K3/025 ,  H05K3/181 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4661 ,  H05K2201/0355 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1152 ,  Y10S205/92 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155

Abstract: A method of manufacturing a printed circuit board is disclosed. A method of manufacturing a printed circuit board, which includes: forming at least one interlayer connector on a first carrier, stacking at least one insulation layer on the first carrier such that the interlayer connector is exposed, removing the first carrier, and forming at least one circuit pattern on the insulation layer such that the circuit pattern is electrically coupled with the interlayer connector, can be used to increase the density of circuit patterns, as the method can provide electrical connection between circuit patterns and vias without using lands.

Abstract translation: 公开了一种制造印刷电路板的方法。 一种制造印刷电路板的方法，包括：在第一载体上形成至少一个层间连接器，在第一载体上堆叠至少一个绝缘层，使得层间连接器暴露，去除第一载体，至少形成 绝缘层上的一个电路图案使得电路图案与层间连接器电耦合，可以用于增加电路图案的密度，因为该方法可以在不使用焊盘的情况下提供电路图案和通孔之间的电连接。

公开(公告)号：US20080225501A1

公开(公告)日：2008-09-18

申请号：US12076274

申请日：2008-03-14

Applicant: Chung-Woo Cho ,  Chang-Sup Ryu ,  Soon-Jin Cho ,  Seung-Chul Kim

Inventor： Chung-Woo Cho ,  Chang-Sup Ryu ,  Soon-Jin Cho ,  Seung-Chul Kim

IPC: H05K7/10 ,  H01K3/10

CPC classification number: H05K3/421 ,  H05K3/108 ,  H05K3/423 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49165

Abstract: A printed circuit board and a manufacturing method thereof are disclosed. The printed circuit board, which includes a first insulation layer, a first via that penetrates the first insulation layer, and a first pad formed on one surface of the first insulation layer, where a whole of or a portion of the first pad is buried in the first via, has a portion of or the whole of the pad buried in the via, so that the contact area between the pad and the via may be increased, and the printed circuit board can be given greater reliability.

Abstract translation: 公开了印刷电路板及其制造方法。 印刷电路板包括第一绝缘层，穿过第一绝缘层的第一通孔和形成在第一绝缘层的一个表面上的第一焊盘，其中第一焊盘的整体或一部分被埋在 第一通孔具有埋在通孔中的焊盘的一部分或全部，从而可以增加焊盘和通孔之间的接触面积，并且可以赋予印刷电路板更高的可靠性。

公开(公告)号：US20080209722A1

公开(公告)日：2008-09-04

申请号：US12068457

申请日：2008-02-06

Applicant: Chong Ho Kim ,  Jong Min Choi ,  Young Hwan Shin

Inventor： Chong Ho Kim ,  Jong Min Choi ,  Young Hwan Shin

IPC: H05K3/42 ,  H05K3/10

CPC classification number: H05K3/428 ,  H05K3/064 ,  H05K2201/09545 ,  H05K2203/0542 ,  H05K2203/1394 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for forming a via hole having a fine hole land with which the density of circuit patterns can be increased. The method includes forming a via hole in a copper clad laminate, coating an etching resist over the copper clad laminate, and forming a circuit pattern on the copper foil of the copper clad laminate; forming a seed layer, coating a photoresist, and exposing an inner wall of the via hole; and forming a plated layer on the inner wall of the via hole and removing the photoresist and the seed layer.

Abstract translation: 一种用于形成通孔的方法，该通孔具有能够增加电路图案的密度的细小空隙区域。 该方法包括在覆铜层压板中形成通孔，在覆铜层压板上涂覆抗蚀剂，并在覆铜层压板的铜箔上形成电路图案; 形成种子层，涂覆光致抗蚀剂，并暴露通孔的内壁; 在通孔的内壁上形成镀层，除去光致抗蚀剂和种子层。

公开(公告)号：US20070130761A1

公开(公告)日：2007-06-14

申请号：US11591586

申请日：2006-11-02

Applicant: Myung Kang ,  Shuhichi Okabe ,  Jung Park ,  Hoe Jung ,  Ji Kim

Inventor： Myung Kang ,  Shuhichi Okabe ,  Jung Park ,  Hoe Jung ,  Ji Kim

IPC: H05K1/11

CPC classification number: H05K1/116 ,  H05K3/0094 ,  H05K3/421 ,  H05K3/428 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/0959 ,  H05K2203/0361 ,  H05K2203/0384 ,  H05K2203/0542 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49133 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Disclosed is a method of manufacturing a printed circuit board having a landless via hole. Specifically, this invention provides a method of manufacturing a printed circuit board having a landless via hole without the upper land of a via hole using a photoresist (P-LPR) which is loaded in the via hole. Therefore, in this invention, since a circuit pattern is formed using only copper of a copper clad laminate, the width thereof is minimized, thus easily realizing a fine circuit pattern. Further, the landless via hole structure is applied, resulting in a highly dense circuit pattern.

Abstract translation: 公开了一种具有无地过孔的印刷电路板的制造方法。 具体而言，本发明提供一种制造印刷电路板的方法，所述印刷电路板具有无通孔通孔，所述无通孔通孔使用装载在所述通孔中的光致抗蚀剂（P-LPR）而不具有通孔的上部焊盘。 因此，在本发明中，由于仅使用覆铜层压板的铜形成电路图案，所以其宽度被最小化，因此容易实现精细电路图案。 此外，施加无地通孔结构，导致高度密集的电路图案。

公开(公告)号：US20070108619A1

公开(公告)日：2007-05-17

申请号：US11274016

申请日：2005-11-15

Applicant: Jun Hsu

Inventor： Jun Hsu

IPC: H01L29/40

CPC classification number: H05K1/112 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H05K1/116 ,  H05K3/244 ,  H05K3/421 ,  H05K2201/09436 ,  H05K2201/09463 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09663 ,  H01L2924/00

Abstract: A bonding pad with high bonding strength to a solder ball and a bump includes a carrier, a wiring layer formed on the carrier, a protection layer formed on top of the wiring layer and a solder mask layer surrounded around the protection layer and the wiring layer to form a bonding pad opening. The protection layer is extended outside the bonding pad opening such that when solder are extended into the bonding pad opening, the solder balls engage with side faces defining the bump pad opening as well as the protection layer outside the bump pad opening and a bonding strength between the bonding pad and the solder performance is increased.

Abstract translation: 具有对焊球和凸块具有高结合强度的接合焊盘包括载体，形成在载体上的布线层，形成在布线层顶部的保护层和围绕保护层和布线层围绕的焊料掩模层 以形成接合焊盘开口。 保护层延伸到接合焊盘开口的外部，使得当焊料延伸到焊盘开口中时，焊球与限定凸块焊盘开口的侧面以及凸块焊盘开口之外的保护层接合， 焊盘和焊料性能提高。

公开(公告)号：US06977348B2

公开(公告)日：2005-12-20

申请号：US10064424

申请日：2002-07-12

Applicant: Kwun-Yao Ho ,  Chen-Yueh Kung

Inventor： Kwun-Yao Ho ,  Chen-Yueh Kung

IPC: H05K3/20 ,  H05K3/28 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K3/4617 ,  H05K3/20 ,  H05K3/281 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T428/24331 ,  Y10T428/24851 ,  Y10T428/24917

Abstract: A laminated substrate structure composed of a plurality of dielectric layers and a plurality of circuit layers stacked with each other. Each of the dielectric layers has a plurality of via studs, and the circuit layers are electrically coupled with each other through the via studs. The laminated substrate structure of the present invention is characterized by adopting the embedded structure landless design that provides high reliability and better adherence. The present invention also provides a laminated substrate manufacture method. The dielectric layers having the patterned circuit and the dielectric layers having the via holes are formed first, and after the dielectric layers having the patterned circuit and the dielectric layers having the via holes are formed, they are aligned and laminated synchronously to complete the manufacture of the laminated substrate.

Abstract translation: 由多个电介质层和彼此堆叠的多个电路层组成的层叠基板结构。 每个电介质层具有多个通孔柱，并且电路层通过通孔螺栓彼此电耦合。 本发明的层压基板结构的特征在于采用提供高可靠性和更好粘附性的嵌入式结构无地设计。 本发明还提供一种层叠基板的制造方法。 首先形成具有图案化电路的电介质层和具有通路孔的电介质层，并且在形成具有图案化电路的电介质层和具有通孔的电介质层的电介质层之后，它们被同步地对准和层压，以完成制造 层压基板。

公开(公告)号：US20050157478A1

公开(公告)日：2005-07-21

申请号：US11062672

申请日：2005-02-23

Applicant: Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/50 ,  H01L23/64 ,  H01L25/16 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46 ,  H01L23/52

CPC classification number: H05K1/115 ,  H01G2/06 ,  H01G4/12 ,  H01G4/224 ,  H01G4/228 ,  H01G4/248 ,  H01G4/40 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/181 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Abstract translation: 片状电容器20设置在印刷电路板10中。以这种方式，IC芯片90和每个片状电容器20之间的距离缩短，并且环路电感减小。 此外，芯片电容器20被容纳在具有大厚​​度的芯基板30中。 因此，印刷电路板的厚度不会变大。

公开(公告)号：US20030183421A1

公开(公告)日：2003-10-02

申请号：US10108219

申请日：2002-03-27

Inventor： Terrance J. Dishongh ,  Carolyn R. McCormick

IPC: H05K001/11

CPC classification number: H05K1/113 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K3/0094 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/429 ,  H05K2201/09545 ,  H05K2201/0959 ,  H05K2201/10234 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A first signal routing layer may be formed on a first surface of a printed circuit board (PCB). An array of interconnections may formed on the first surface of the PCB, the array of interconnections comprising at least one padless via formed within the PCB, the at least one padless via extending from the first signal routing layer to at least one conductive plane and/or a second signal routing layer. The at least one padless via may be in electrical contact with the at least one conductive plane and/or a conductive trace on the second signal routing layer. A component may be attached to the PCB, with a solder interconnection between the at least one padless via and a contact pad on a bottom surface of the component. The component may be, for example, an electronic component such as a ball grid array (BGA) component or a leadless surface mount component.

Abstract translation: 第一信号布线层可以形成在印刷电路板（PCB）的第一表面上。 互连阵列可以形成在PCB的第一表面上，互连阵列包括形成在PCB内的至少一个无衬垫通孔，从第一信号布线层延伸到至少一个导电平面的至少一个无衬垫通孔和/ 或第二信号路由层。 所述至少一个无衬垫通孔可以与所述至少一个导电平面和/或所述第二信号布线层上的导电迹线电接触。 组件可以附接到PCB，其中焊料互连在该至少一个无衬垫通孔和该部件的底部表面上的接触焊盘之间。 组件可以是例如电子部件，例如球栅阵列（BGA）部件或无引线表面安装部件。

公开(公告)号：US12131985B2

公开(公告)日：2024-10-29

申请号：US17470519

申请日：2021-09-09

Applicant: CORNING INCORPORATED

Inventor： Mandakini Kanungo ,  Prantik Mazumder ,  Chukwudi Azubuike Okoro ,  Ah-Young Park ,  Scott Christopher Pollard ,  Rajesh Vaddi

IPC: C25D3/38 ,  C03C3/06 ,  C03C15/00 ,  C03C17/06 ,  C03C17/10 ,  C03C23/00 ,  C23C14/18 ,  C23C18/38 ,  C23C28/02 ,  H01L21/48 ,  H01L21/768 ,  H01L23/15 ,  H01L23/48 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/38 ,  C03C3/076 ,  C25D7/12 ,  H01L23/00 ,  H01L23/492 ,  H05K3/00 ,  H05K3/42

CPC classification number: H01L23/49827 ,  C03C3/06 ,  C03C15/00 ,  C03C17/06 ,  C03C17/10 ,  C03C23/0025 ,  C23C14/18 ,  C23C18/38 ,  C23C28/02 ,  H01L21/76877 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49838 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/388 ,  C03C3/076 ,  C03C2218/115 ,  C25D3/38 ,  C25D7/123 ,  H01L21/486 ,  H01L23/4924 ,  H01L23/49866 ,  H01L23/564 ,  H05K3/002 ,  H05K3/0029 ,  H05K3/0055 ,  H05K3/423 ,  H05K3/425 ,  H05K3/428 ,  H05K2201/068 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/0989 ,  H05K2201/10378 ,  H05K2203/1194 ,  H05K2203/1361 ,  H05K2203/143 ,  H05K2203/1438 ,  H05K2203/162 ,  Y10T428/24273 ,  Y10T428/24479 ,  Y10T428/24851 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: According to various embodiments described herein, an article comprises a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and a via extending through the substrate from the first major surface to the second major surface over an axial length in an axial direction. The article further comprises a helium hermetic adhesion layer disposed on the interior surface; and a metal connector disposed within the via, wherein the metal connector is adhered to the helium hermetic adhesion layer. The metal connector coats the interior surface of the via along the axial length of the via to define a first cavity from the first major surface to a first cavity length, the metal connector comprising a coating thickness of less than 12 μm at the first major surface. Additionally, the metal connector coats the interior surface of the via along the axial length of the via to define a second cavity from the second major surface to a second cavity length, the metal connector comprising a coating thickness of less than 12 μm at the second major surface and fully fills the via between the first cavity and the second cavity.

公开(公告)号：US20240314940A1

公开(公告)日：2024-09-19

申请号：US18604301

申请日：2024-03-13

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Ki Wook LEE ,  Chien Jen WANG

IPC: H05K3/42 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/429 ,  H05K1/115 ,  H05K3/0047 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2203/107

Abstract: According to certain aspects, devices and methods can be provided for forming packaging substrates having ringless vias. For instance, a method of forming one or more vias in a packaging substrate can include: laminating a plurality of layers of a packaging substrate; drilling a via hole through the plurality of layers using a through drill, the plurality of layers not including a capture pad or ring along a path of the through drill for drilling the via hole; and forming a via in the via hole using a plating process.