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公开(公告)号：US11903143B2
公开(公告)日：2024-02-13
申请号：US17645247
申请日：2021-12-20
Applicant: Microsoft Technology Licensing, LLC
CPC classification number: H05K3/363 , H05K1/0277 , H05K1/111 , H05K1/115 , H05K1/144 , H05K2201/09609 , H05K2203/043
Abstract: Examples are disclosed related to forming solder joints between printed circuits by using radiant heat. One example provides a method of manufacturing an electronic device, the method comprising aligning a contact of a first printed circuit with a via of a second printed circuit. The method further comprises applying radiant heat via an infrared light source to a second surface of the second printed circuit, the radiant heat incident on the via to cause the via to conduct heat to solder located at an interface of the contact and the via, and after heating the solder to reflow, cooling the solder, thereby forming a solder joint between the contact of the first printed circuit and the via of the second printed circuit.
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公开(公告)号：US11696390B2
公开(公告)日：2023-07-04
申请号：US17100121
申请日：2020-11-20
Applicant: QUALCOMM Incorporated
Inventor： Jeahyeong Han , Suhyung Hwang , Mina Iskander , Rajneesh Kumar , Darryl Sheldon Jessie
CPC classification number: H05K1/0219 , H01Q1/2283 , H01Q1/48 , H01Q1/526 , H01Q21/061 , H05K1/0225 , H05K1/0227 , H05K1/0278 , H01Q21/29 , H01Q23/00 , H05K1/181 , H05K2201/09609 , H05K2201/09681 , H05K2201/10098
Abstract: Systems for shielding bent signal lines provide ways to couple different antenna arrays for radio frequency (RF) integrated circuits (ICs) (RFICs) associated therewith where the antenna arrays are oriented in different directions. Because the antenna arrays are oriented in different directions, the antenna structures containing the antennas may be arranged in different planes, and signal lines extending therebetween may include a bend. To prevent electromagnetic interference (EMI) or electromagnetic crosstalk (EMC) from negatively impacting signals on the signal lines, the signal lines may be shielded. The shields may further include vias connecting the mesh ground planes and positioned exteriorly of the signal lines. The density of the vias may be varied to provide a desired rigidity in planes containing the antenna arrays while providing a desired flexibility at a desired bending location in the signal lines to help bending process accuracy.
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公开(公告)号：US20230209715A1
公开(公告)日：2023-06-29
申请号：US18069805
申请日：2022-12-21
Applicant: NICHIA CORPORATION
Inventor： Soichiro MIURA
CPC classification number: H05K1/181 , H01S3/2383 , H05K1/113 , H05K1/0274 , H05K2201/09409 , H05K2201/09609 , H05K2201/10121 , H05K2201/10522
Abstract: A wiring board includes: an insulating member having a first upper surface, and a second upper surface located higher than the first upper surface; and a first wiring layer located on the first upper surface. The first upper surface has a wiring region that does not overlap with the second upper surface in a top view, and that is located in an exposed region. The first wiring layer extends from the wiring region to a connecting region that is connected to the wiring region, that overlaps with the second upper surface in a top view, and that is not exposed. The first wiring layer comprises a first pad portion located in the wiring region, and a first pattern portion located in the connecting region.
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公开(公告)号：US20230199971A1
公开(公告)日：2023-06-22
申请号：US17645247
申请日：2021-12-20
Applicant: Microsoft Technology Licensing, LLC
CPC classification number: H05K3/363 , H05K1/0277 , H05K1/111 , H05K1/115 , H05K1/144 , H05K2201/09609 , H05K2203/043
Abstract: Examples are disclosed related to forming solder joints between printed circuits by using radiant heat. One example provides a method of manufacturing an electronic device, the method comprising aligning a contact of a first printed circuit with a via of a second printed circuit. The method further comprises applying radiant heat via an infrared light source to a second surface of the second printed circuit, the radiant heat incident on the via to cause the via to conduct heat to solder located at an interface of the contact and the via, and after heating the solder to reflow, cooling the solder, thereby forming a solder joint between the contact of the first printed circuit and the via of the second printed circuit.
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85.发明申请公开(公告)号：US20190008033A1
公开(公告)日：2019-01-03
申请号：US16025641
申请日：2018-07-02
Applicant: INKTEC CO., LTD.
Inventor： KWANG-CHOON CHUNG , BYUNG WOONG MOON
CPC classification number: H05K1/0219 , H01B7/08 , H01R12/79 , H05K1/028 , H05K1/115 , H05K1/118 , H05K3/422 , H05K3/425 , H05K9/0098 , H05K2201/0154 , H05K2201/0715 , H05K2201/093 , H05K2201/09609 , H05K2201/09681 , H05K2203/072
Abstract: The present disclosure relates a printed circuit board having an EMI shielding function. In an example embodiment, the printed circuit board includes a substrate, a signal unit disposed on the substrate, a ground unit disposed in parallel with the signal unit, an insulation layer disposed above the substrate and covering the signal unit and the ground unit, an EMI shielding layer disposed on the insulation layer and under the substrate, respectively, and a shielding bridge passing through the substrate and the insulation layer at opposite sides of the signal unit and electrically connecting the EMI shielding layer disposed on the insulation layer to the EMI shielding layer disposed under the substrate.
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Patent Agency Ranking
86.发明申请公开(公告)号：US20180301428A1
公开(公告)日：2018-10-18
申请号：US15949746
申请日：2018-04-10
Applicant: Rajen Manicon Murugan , Minhong Mi , Gary Paul Morrison , Jie Chen , Kenneth Robert Rhyner , Stanley Craig Beddingfield , Chittranjan Mohan Gupta , Django Earl Trombley
Inventor： Rajen Manicon Murugan , Minhong Mi , Gary Paul Morrison , Jie Chen , Kenneth Robert Rhyner , Stanley Craig Beddingfield , Chittranjan Mohan Gupta , Django Earl Trombley
CPC classification number: H01L23/66 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2223/6627 , H01L2223/6655 , H01L2223/6677 , H01L2223/6683 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/1423 , H01L2924/15173 , H01L2924/15311 , H01L2924/30111 , H01Q1/2283 , H01Q1/3233 , H01Q23/00 , H05K1/0222 , H05K1/0243 , H05K1/0245 , H05K1/0251 , H05K1/181 , H05K2201/09609 , H05K2201/10734 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599
Abstract: A millimeter wave integrated circuit (IC) chip. The IC chip comprises an IC die and a wire bond ball grid array package encapsulating the IC die. The wire bond ball grid array package comprises a solder ball array, a millimeter wave transmit channel, and a millimeter wave receive channel, wherein each millimeter wave transmit and receive channel electrically couples the IC die to a signal ball of the solder ball array and is configured to resonate at an operating frequency band of the millimeter wave IC chip.
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公开(公告)号：US10014244B2
公开(公告)日：2018-07-03
申请号：US15214532
申请日：2016-07-20
Applicant: Dai Nippon Printing Co., Ltd.
Inventor： Takamasa Takano
IPC: H05K1/16 , H01L23/498 , H01L21/48 , H01L21/768 , H01L23/14 , H01L23/48 , H05K1/11 , H05K3/42 , H01L23/00 , H05K3/44
CPC classification number: H01L23/49827 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49833 , H01L23/49838 , H01L23/49866 , H01L23/49894 , H01L24/17 , H01L2224/05647 , H01L2224/16225 , H01L2224/16235 , H01L2924/01024 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/15747 , H01L2924/15786 , H01L2924/1579 , H05K1/113 , H05K3/426 , H05K3/445 , H05K2201/09436 , H05K2201/09581 , H05K2201/09609 , H05K2201/09836 , H05K2201/09854 , H05K2201/10378 , H05K2203/0733 , H05K2203/1178 , Y10T29/49117 , Y10T29/49124 , Y10T29/49165
Abstract: A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.
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公开(公告)号：US20180180828A1
公开(公告)日：2018-06-28
申请号：US15850124
申请日：2017-12-21
Applicant: Hisense Broadband Multimedia Technologies, Co., Ltd. , Hisense Broadband Multimedia Technologies, Ltd.
Inventor： Wei Zhao , Dongmei Yu
CPC classification number: G02B6/4277 , G02B6/4279 , G02B6/428 , G02B6/4281 , H05K1/0219 , H05K1/115 , H05K1/118 , H05K1/181 , H05K1/189 , H05K2201/0715 , H05K2201/09027 , H05K2201/093 , H05K2201/09609 , H05K2201/09618 , H05K2201/10121 , H05K2201/10522
Abstract: The present disclosure provides an optical module, including a circuit board, an optical chip and an optical chip driver. Where the circuit board may include a first layer provided with a first ground plane, a second layer provided with a second ground plane and a high-speed signal line between the first ground plane and the second ground plane. at least a part of the high-speed signal line is enclosed in a shielding cage which is formed by the first ground plane, the second ground plane and a plurality of metal vias connecting the first ground plane and the second ground plane in a way that the at least a part of the high-speed signal line is electromagnetic shielded by the shielding cage.
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公开(公告)号：US20180027668A1
公开(公告)日：2018-01-25
申请号：US15541687
申请日：2015-12-17
Applicant: FUJIKURA LTD.
Inventor： Masahiro Kaizu , Masateru Ichikawa
CPC classification number: H05K3/4644 , H01B1/22 , H05K1/115 , H05K3/10 , H05K3/12 , H05K2201/0137 , H05K2201/0929 , H05K2201/09609 , H05K2203/0195 , H05K2203/0776 , H05K2203/1131
Abstract: A method of manufacturing a conductive layer on a support body includes a first process of forming a precursor layer containing at least one of metal particles and metal oxide particles on the support body; a second process of forming a sintering layer by irradiating an electromagnetic wave pulse on the precursor layer; and a third process of compressing the sintering layer. The conductive layer is formed by repeating the first to third processes “N” times, where “N” denotes a natural number equal to or greater than 2, on the same location of the support body, and the third process performed in the first to (N−1)th operations includes forming a surface of the sintering layer in an uneven shape.
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公开(公告)号：US09867277B2
公开(公告)日：2018-01-09
申请号：US13654450
申请日：2012-10-18
Applicant: Infineon Technologies Austria AG
Inventor： Martin Standing , Andrew Roberts
IPC: H05K1/18 , H05K1/02 , H01L23/538 , H05K3/42 , H05K3/46
CPC classification number: H05K1/0207 , H01L23/5389 , H01L2924/0002 , H05K1/0265 , H05K1/186 , H05K3/429 , H05K3/4602 , H05K2201/09545 , H05K2201/09609 , H05K2201/10166 , H05K2201/10416 , H05K2201/10492 , H05K2201/10515 , Y10T29/49128 , H01L2924/00
Abstract: Representative implementations of devices and techniques provide improved electrical performance of components, such as chip dice, for example, disposed on different layers of a multi-layer printed circuit board (PCB). In an example, the components may be embedded within layers of the PCB. An insulating layer located between two component layers or sets of layers includes a conductive portion that may be strategically located to provide electrical connectivity between the components. The conductive portion may also be arranged to improve thermal conductivity between points of the PCB.
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