公开(公告)号：US20140048313A1

公开(公告)日：2014-02-20

申请号：US13962248

申请日：2013-08-08

Applicant: Bridge Semiconductor Corporation

Inventor： Wei-Kuang PAN ,  Charles W.C. LIN ,  Chia-Chung WANG

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  H01L23/3677 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/73265 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/0209 ,  H05K3/0052 ,  H05K3/4652 ,  H05K2201/09181 ,  H05K2201/09363 ,  H05K2201/09509 ,  H05K2201/09781 ,  H05K2201/10416 ,  H05K2203/063 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A thermally enhanced wiring board with thermal pad and electrical post includes a metal slug, a metal pillar, a patterned interconnect substrate, an adhesive, a build-up circuitry and optionally a plated through hole. The metal slug and the metal pillar extend into apertures of the patterned interconnect substrate and are electrically connected to the build-up circuitry. The build-up circuitry covers the metal slug, the metal pillar and the patterned interconnect substrate and can provide signal routing. The metal slug can provide thermal contact surface, and the metal pillar can serve as power/ground plane or signal vertical transduction pathway.

Abstract translation: 具有热垫和电焊柱的热增强布线板包括金属块，金属柱，图案化互连衬底，粘合剂，积聚电路和任选的电镀通孔。 金属块和金属柱延伸到图案化的互连衬底的孔中并且电连接到积聚电路。 积聚电路覆盖金属块，金属柱和图案化的互连衬底，并且可以提供信号路由。 金属块可以提供热接触表面，金属柱可以用作电源/接地平面或信号垂直传导通路。

公开(公告)号：US20140034363A1

公开(公告)日：2014-02-06

申请号：US13957089

申请日：2013-08-01

Applicant: Samtec, Inc.

Inventor： Gary Ellsworth BIDDLE

IPC: H05K1/02

CPC classification number: H01P3/081 ,  H01P3/026 ,  H01P5/028 ,  H01P5/08 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/0228 ,  H05K1/0237 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/115 ,  H05K1/118 ,  H05K1/14 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/097 ,  H05K2201/09781 ,  H05K2201/0979

Abstract: A substrate including a first transmission line arranged to transmit electrical signals and including first and second traces and a first dielectric layer. The first and second traces are separated from each other by the first dielectric layer. A printed circuit board includes a first transmission line arranged to transmit electrical signals and including first, second, and third traces; and a first dielectric layer. The first and second traces are separated from the third trace by the first dielectric layer.

公开(公告)号：US20140029222A1

公开(公告)日：2014-01-30

申请号：US14043381

申请日：2013-10-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoichi Saito ,  Toru Yoshioka

IPC: H01L23/31 ,  H05K1/18

CPC classification number: H01L23/3121 ,  H01L2224/16225 ,  H01L2924/15313 ,  H05K1/184 ,  H05K1/186 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/09781 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611

Abstract: The present invention provides a chip component-embedded resin multilayer substrate including a laminating body obtained by laminating a plurality of resin layers, a predetermined wiring conductor disposed in the laminating body, and a chip component embedded in the laminating body and having a side terminal electrode. A guarding member electrically isolated from the wiring conductor is provided to cover at least a part of a boundary between the side terminal electrode and the resin layers when viewed from a lamination direction of the laminating body, and the guarding member is formed from a material having a melting point higher than a temperature at which the resin layer begins to flow.

Abstract translation: 本发明提供一种片状部件嵌入式树脂多层基板，其包括层叠多个树脂层而得到的层叠体，配置在层叠体中的规定布线导体和嵌入层叠体的芯片部件，具有侧端子电极 。 设置与布线导体电绝缘的防护部件，以覆盖从层叠体的层叠方向观察时的侧端子电极与树脂层的边界的至少一部分，并且防护部件由具有 熔点高于树脂层开始流动的温度。

公开(公告)号：US08633397B2

公开(公告)日：2014-01-21

申请号：US12860301

申请日：2010-08-20

Applicant: Jin-Soo Jeong ,  Doo-hwan Lee ,  Hwa-Sun Park ,  Jae-Kul Lee ,  Yul-Kyo Chung

Inventor： Jin-Soo Jeong ,  Doo-hwan Lee ,  Hwa-Sun Park ,  Jae-Kul Lee ,  Yul-Kyo Chung

IPC: H05K1/16

CPC classification number: H05K3/007 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/0032 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2203/0156 ,  H05K2203/0554 ,  H05K2203/1572 ,  Y10T29/49124 ,  H01L2924/00

Abstract: A method of processing a cavity of a core substrate is disclosed. The method of processing a cavity of a core substrate in accordance with an embodiment of the present invention can include: forming a first processing area on one surface of a core substrate, the first processing area being demarcated by a circuit pattern; forming a second processing area on the other surface of the core substrate, the second processing area being demarcated by a circuit pattern; and processing a cavity by removing the entire first processing area from the one surface of the core substrate.

Abstract translation: 公开了一种处理芯基板的空腔的方法。 根据本发明的实施例的处理芯基板的空腔的方法可以包括：在芯基板的一个表面上形成第一处理区域，第一处理区域由电路图案划定; 在所述芯基板的另一表面上形成第二处理区域，所述第二处理区域由电路图案划定; 以及通过从芯基板的一个表面去除整个第一处理区域来处理空腔。

公开(公告)号：US20140017938A1

公开(公告)日：2014-01-16

申请号：US13935292

申请日：2013-07-03

Applicant: PANASONIC CORPORATION

Inventor： Hiroshi IWANO ,  Mitsuru IIDA ,  Daisuke SATO ,  Hidetoshi TAKEYAMA

IPC: H01R12/61

CPC classification number: H01R12/613 ,  H01R12/79 ,  H05K1/11 ,  H05K1/114 ,  H05K1/117 ,  H05K3/0038 ,  H05K3/365 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09409 ,  H05K2201/09427 ,  H05K2201/09445 ,  H05K2201/0949 ,  H05K2201/09509 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10189 ,  H05K2201/2009 ,  H05K2201/2072 ,  H05K2203/167

Abstract: A socket (female connector) used for a connector assembly includes a film substrate constituted by a flexible thin board made of insulation material. The film substrate is provided with connection through holes adapted to be inserted therein connection posts of a header (male connector). Connection pads are formed on a first surface of the film substrate around respective connection through holes. The connection pads include a first pad and a second pad. The film substrate is provided on the first surface with a first patterned conductor connected to the first pad and a third patterned conductor connected to the second pad. The third patterned conductor is connected to a second patterned conductor formed on a second surface of the film substrate by means of a blind via that is formed by boring the film substrate from the second surface so as to reach the third patterned conductor.

Abstract translation: 用于连接器组件的插座（母连接器）包括由绝缘材料制成的柔性薄板构成的薄膜基片。 薄膜基片设置有适于插入插头（公连接器）的连接柱中的连接通孔。 连接衬垫围绕各个连接通孔形成在薄膜基片的第一表面上。 连接焊盘包括第一焊盘和第二焊盘。 薄膜基板在第一表面上设置有连接到第一焊盘的第一图案化导体和连接到第二焊盘的第三图案化导体。 第三图案化导体通过盲孔通过第二图案导体连接到形成在膜基板的第二表面上的第二图案化导体，所述盲孔通过从第二表面镗孔而形成，以到达第三图案化导体。

公开(公告)号：US20130299219A1

公开(公告)日：2013-11-14

申请号：US13941066

申请日：2013-07-12

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Shunsuke Chisaka ,  Hiroshi Somada ,  Kosuke Nakano ,  Noboru Kato

IPC: H05K1/09 ,  H05K3/42 ,  H05K1/11

CPC classification number: H05K1/092 ,  H01L2224/16225 ,  H01L2924/1533 ,  H05K1/0271 ,  H05K1/115 ,  H05K1/185 ,  H05K3/0052 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0305 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10636 ,  H05K2203/0554 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/49165

Abstract: The present invention provides a multilayer circuit board that includes a plurality of resin layers, conductive wiring layers, and via-hole conductors. Each of the resin layers includes a resin sheet containing a resin and a conductive wiring layer disposed on at least one surface of the resin sheet. The via-hole conductors contain an intermetallic compound having a melting point of 300° C. or more produced by a reaction between a first metal composed of Sn or an alloy containing 70% by weight or more Sn and a second metal composed of a Cu—Ni alloy or a Cu—Mn alloy. The second metal has a higher melting point than the first metal.

Abstract translation: 本发明提供一种多层电路板，其包括多个树脂层，导电布线层和通孔导体。 每个树脂层包括含有树脂的树脂片和布置在树脂片的至少一个表面上的导电布线层。 通孔导体含有由Sn组成的第一金属或含有70重量％以上的Sn的合金与由Cu组成的第二金属之间的反应产生的熔点为300℃以上的熔点的金属间化合物 -Ni合金或Cu-Mn合金。 第二金属具有比第一金属更高的熔点。

公开(公告)号：US08574449B2

公开(公告)日：2013-11-05

申请号：US13462399

申请日：2012-05-02

Applicant: Hirohito Watanabe ,  Taiji Ogawa ,  Eriko Tomonaga

Inventor： Hirohito Watanabe ,  Taiji Ogawa ,  Takaomi Tomonaga

IPC: B44C1/22

CPC classification number: H05K1/0269 ,  H05K3/06 ,  H05K2201/09781 ,  H05K2203/1545 ,  H05K2203/163

Abstract: Quickly making changes to etching conditions suppresses the production yield of printed wiring boards from being deteriorated. Disclosed is a method comprising: an etching step that comprises: preparing a conductor-clad base material continuous in a certain direction, the conductor-clad base material (1) having an insulating layer and one or more conductive layers formed on main surfaces of the insulating layer; and subjecting a predetermined region of a conductor layer of one main surface of the conductor-clad base material (1) to an etching process thereby to form a wiring pattern (1a) to be of a product and an inspection pattern (1b) to be used for inspection; a measuring step that measures a line width of the inspection pattern after the etching step; and a control step that controls an etching condition in the etching step based on the measured line width.

Abstract translation: 迅速改变蚀刻条件抑制了印刷电路板的生产成本的恶化。 公开了一种方法，包括：蚀刻步骤，包括：制备在一定方向上连续的导体包覆基材，所述导体包覆基材（1）具有绝缘层和形成在所述导体包覆基材的主表面上的一个或多个导电层 绝缘层; 并且对导体包覆基材（1）的一个主表面的导体层的预定区域进行蚀刻处理，从而形成作为产品的布线图案（1a）和检查图案（1b） 用于检验; 测量步骤，其测量所述蚀刻步骤之后的所述检查图案的线宽; 以及控制步骤，其基于所测量的线宽来控制蚀刻步骤中的蚀刻条件。

公开(公告)号：US08525333B2

公开(公告)日：2013-09-03

申请号：US12736191

申请日：2009-03-17

Applicant: Yoshifumi Kanetaka

Inventor： Yoshifumi Kanetaka

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/15311 ,  H05K3/321 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2924/00

Abstract: An electronic device includes the electronic element, the interposer substrate, on one surface of which the electronic element is mounted, and the interconnection substrate, on one surface of which the interposer substrate is mounted. One portion of the connection parts is an electrical connection part that electrically interconnects the interposer substrate and the interconnection substrate. The remaining portion is a dummy connection part that produces no functional deficiency even when the dummy connection part does not electrically interconnect the interposer substrate with the interconnection substrate. The dummy connection part includes at least one of the connection parts that at least partially overlap with the electronic element in a plan projection and are preferably arranged along an outer rim of the plan projection of the electronic element.

Abstract translation: 电子设备包括电子元件，插入器基板，其一个表面上安装有电子元件，以及互连基板，其一个表面上安装有插入器基板。 连接部分的一部分是将插入器基板和互连基板电连接的电连接部分。 剩余部分是虚拟连接部分，即使虚拟连接部分不将互连基板与互连基板电气互连，也不产生功能缺陷。 虚拟连接部分包括在平面突起中至少部分地与电子元件重叠的连接部分中的至少一个，并且优选地沿着电子元件的平面突起的外边缘布置。

公开(公告)号：US08519271B2

公开(公告)日：2013-08-27

申请号：US12485615

申请日：2009-06-16

Applicant: Harutoshi Oikawa ,  Kiyohiro Kimura

Inventor： Harutoshi Oikawa ,  Kiyohiro Kimura

IPC: H05K1/00

CPC classification number: H05K3/361 ,  H05K3/281 ,  H05K3/323 ,  H05K3/421 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/097 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2203/1572

Abstract: A flexible printed circuit includes: a flexible substrate extending from a first end section to a second end section, and having an opening or a notch in proximity to the first end section; a first wiring layer extending from the first end section to the second end section so as to avoid the opening or the notch; a second wiring layer extending from the first end section to the second end section so as to block the opening or the notch; a first conductive member being formed opposed to the flexible substrate in relation to the first wiring layer and at least in proximity to the first end section in a region opposed to the first wiring layer, and being electrically connected to the first wiring layer; and a second conductive member electrically connected to the second wiring layer via the opening or the notch.

Abstract translation: 柔性印刷电路包括：柔性基板，其从第一端部延伸到第二端部，并且具有靠近第一端部的开口或凹口; 第一布线层，从第一端部延伸到第二端部，以避免开口或凹口; 第二布线层，其从所述第一端部延伸到所述第二端部，以阻挡所述开口或所述凹口; 第一导电构件，其与所述柔性基板相对于所述第一布线层形成，并且在与所述第一布线层相对的区域中至少靠近所述第一端部，并且电连接到所述第一布线层; 以及通过所述开口或所述凹口与所述第二布线层电连接的第二导电构件。

公开(公告)号：US20130213699A1

公开(公告)日：2013-08-22

申请号：US13857167

申请日：2013-04-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shunsuke CHISAKA

IPC: H05K1/18 ,  H05K3/32

CPC classification number: H05K1/185 ,  H05K1/182 ,  H05K1/186 ,  H05K3/32 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/09527 ,  H05K2201/09781 ,  H05K2203/063 ,  Y10T29/49139

Abstract: A substrate includes a built-in component that suppresses resin flow occurring in the case of thermocompression bonding in a region where vias and wiring conductors are provided and that reduces the occurrence of via defects and wiring-conductor defects. The resin flow occurring in an outer side portion of a frame-shaped electrode is suppressed in the case of thermocompression bonding by encircling the periphery of a built-in component with the frame-shaped electrode. Because of this structure, the occurrence of defects in vias and wiring conductors arranged in an outer side portion of the frame-shaped electrode may be reduced.

Abstract translation: 基板包括抑制在设置有通孔和布线导体的区域中的热压接时发生的树脂流动并且减少了通孔缺陷和布线导体缺陷的发生的内置部件。 在通过用框状电极环绕内置部件的周围的热压接的情况下，在框状电极的外侧部分发生的树脂流被抑制。 由于这种结构，可以减少布置在框架状电极的外侧部分中的通孔和布线导体中的缺陷的发生。