公开(公告)号：US08440915B2

公开(公告)日：2013-05-14

申请号：US12915852

申请日：2010-10-29

Applicant: Masayuki Nagamatsu ,  Kiyoshi Shibata ,  Takanori Hayashi

Inventor： Masayuki Nagamatsu ,  Kiyoshi Shibata ,  Takanori Hayashi

IPC: H05K1/11

CPC classification number: H05K3/3452 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/0367 ,  H05K2201/10515 ,  H05K2201/10734 ,  H05K2203/0588 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is of a PoP structure such that first electrode portions provided on a first device mounting board constituting a first semiconductor module and second electrode portions provided in a second semiconductor module are joined together by solder balls. A first insulating layer having an opening is provided on one main surface of an insulating resin layer which is a substrate, and an electrode portion, whose top portion protrudes above the top surface of the first insulating layer, is formed in the opening. A second insulating layer is provided on top of the first insulating layer in the periphery of the top portion of the first electrode portion; the second insulting layer is located slightly apart from the top portion of the first electrode portion. The first electrode portion is shaped such that the top portion is formed by a curved surface or formed by a curved surface and a plane surface smoothly connected to the curved surface.

Abstract translation: 半导体器件具有PoP结构，使得设置在构成第一半导体模块的第一器件安装板上的第一电极部分和设置在第二半导体器件中的第二电极部分通过焊球接合在一起。 具有开口的第一绝缘层设置在作为基板的绝缘树脂层的一个主表面上，并且其顶部突出于第一绝缘层的顶表面上方的电极部分形成在开口中。 在第一电极部分的顶部周边的第一绝缘层的顶部上设置第二绝缘层; 第二绝缘层位于与第一电极部分的顶部稍微分开的位置。 第一电极部分被成形为使得顶部由弯曲表面形成或由曲面形成并且平坦表面平滑地连接到弯曲表面。

公开(公告)号：US20130105943A1

公开(公告)日：2013-05-02

申请号：US13458059

申请日：2012-04-27

Applicant: Chien-Kuang Lai ,  Chun-Chih Huang

Inventor： Chien-Kuang Lai ,  Chun-Chih Huang

IPC: H01L27/08 ,  H01L21/50

CPC classification number: H01G4/30 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/642 ,  H01L28/40 ,  H01L2924/0002 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10015 ,  H05K2201/10515 ,  H01L2924/00

Abstract: A packaging substrate includes: a substrate having a core layer, a cavity penetrating the core layer and circuit layers formed on surfaces of the core layer; a first capacitor disposed in the cavity; a bonding layer formed on the first capacitor in the cavity of the substrate; a second capacitor disposed on the bonding layer so as to be received in the cavity; and a dielectric layer formed on the substrate and in the cavity for covering the first and second capacitors. By stacking the first and second capacitors in the cavity through the bonding layer, the single core layer is embedded with two layers of the capacitors to thereby meet the multi-function requirement.

Abstract translation: 封装基板包括：具有芯层的基板，穿透芯层的空腔和形成在芯层表面上的电路层; 设置在所述空腔中的第一电容器; 形成在所述基板的空腔中的所述第一电容器上的接合层; 设置在所述接合层上以便容纳在所述空腔中的第二电容器; 以及形成在所述基板上和所述空腔中的用于覆盖所述第一和第二电容器的电介质层。 通过结合层将空腔中的第一和第二电容器堆叠起来，单芯层嵌有两层电容器，从而满足多功能要求。

公开(公告)号：US08363418B2

公开(公告)日：2013-01-29

申请号：US13163502

申请日：2011-06-17

Applicant: Morgan Johnson ,  Frederick G. Weiss

Inventor： Morgan Johnson ,  Frederick G. Weiss

IPC: H05K7/00

CPC classification number: G06F13/16 ,  G06F1/32 ,  G06F13/4068 ,  G11C5/04 ,  H01L23/32 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K1/147 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/095 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10522 ,  Y02D10/151 ,  Y10T29/4913 ,  H01L2924/00

Abstract: An interposer substrate includes an array of interconnects in the interposer substrate, the array of connectors arranged in accordance with an array of interconnects for a processor on a circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one connector in the array of interconnects, the conductive trace arranged parallel to the interposer substrate such that no electrical connection exists between the connector in the interposer substrate and a corresponding one of the interconnects for the processor on the circuit substrate, and at least one peripheral circuit residing on the interposer substrate in electrical connection with the conductive trace.

Abstract translation: 插入器衬底包括插入器衬底中的互连阵列，所述连接器阵列根据用于电路衬底上的处理器的互连阵列布置，所述插入器衬底中的至少一个导电迹线与至少一个连接器 所述互连阵列，所述导电迹线平行于所述插入器基板布置，使得在所述插入器基板中的所述连接器与所述电路基板上的所述处理器的相应的一个互连件之间不存在电连接;以及至少一个外围电路， 所述插入器衬底与所述导电迹线电连接。

公开(公告)号：US20130001709A1

公开(公告)日：2013-01-03

申请号：US13172604

申请日：2011-06-29

Applicant: Chia-Ming Liu

Inventor： Chia-Ming Liu

IPC: H01L29/84 ,  H01L21/60

CPC classification number: H05K1/181 ,  B81C1/0023 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1461 ,  H05K1/0201 ,  H05K3/3431 ,  H05K2201/10083 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10537 ,  H05K2203/041 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00

Abstract: A sensing unit package with reduced size and improved thermal sensing capabilities. An exemplary package includes a printed circuit board with a plurality of electrical traces, an application-specific integrated circuit (Analog ASIC) chip, and a micromachined sensor formed on a microelectromechanical system (MEMS) die. The Analog ASIC chip is electrically and mechanically attached to the printed circuit board. The MEMS die is in direct electrical communication with only a portion of the electrical traces of the printed circuit board and is mechanically and thermally attached directly to the Analog ASIC chip. A thermally conducting compound is located between the MEMS die and the Analog ASIC chip. One or more solder balls electrically attach the Analog ASIC chip to the printed circuit board and one or more solder traces electrically attach the MEMS die to the printed circuit board.

Abstract translation: 感测单元封装尺寸减小，热感测能力更强。 示例性封装包括具有多个电迹线的印刷电路板，专用集成电路（Analog ASIC）芯片，以及形成在微机电系统（MEMS））芯片上的微机械传感器。 模拟ASIC芯片电气和机械连接到印刷电路板。 MEMS管芯与印刷电路板的仅一部分电迹线直接电连通，并且机械和热连接到模拟ASIC芯片。 导热化合物位于MEMS管芯和模拟ASIC芯片之间。 一个或多个焊球将模拟ASIC芯片电连接到印刷电路板，并且一个或多个焊迹迹线将MEMS管芯电连接到印刷电路板。

公开(公告)号：US08339794B2

公开(公告)日：2012-12-25

申请号：US12713282

申请日：2010-02-26

Applicant: Hyo-Jae Bang ,  Jung-Hyeon Kim

Inventor： Hyo-Jae Bang ,  Jung-Hyeon Kim

IPC: H05K5/00

CPC classification number: H05K1/18 ,  H01G9/08 ,  H01G9/155 ,  H01L2224/16227 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/19106 ,  H05K3/325 ,  H05K3/403 ,  H05K5/0091 ,  H05K2201/09181 ,  H05K2201/10015 ,  H05K2201/10515 ,  H01L2224/0401

Abstract: A casing to support a solid state device SSD therein and super capacitors therein to be electronically connected together.

Abstract translation: 用于支撑其中的固态器件SSD的壳体和其中的超级电容器以电子方式连接在一起。

公开(公告)号：US08319230B1

公开(公告)日：2012-11-27

申请号：US13041425

申请日：2011-03-06

Applicant: Achyut Kumar Dutta

Inventor： Achyut Kumar Dutta

IPC: H01L21/00

CPC classification number: G02B6/12002 ,  G02B6/122 ,  G02B6/32 ,  G02B6/4214 ,  G02B6/4224 ,  G02B6/4257 ,  G02B6/4268 ,  G02B6/4279 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/12147 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/167 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/02248 ,  H01S5/02272 ,  H01S5/183 ,  H05K1/0274 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/10121 ,  H05K2201/10515 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099

Abstract: An optoelectronics chip-to-chip interconnects system is provided, including at least one packaged chip to be connected on the printed-circuit-board with at least one other packaged chip, optical-electrical (O-E) conversion mean, waveguide-board, and (PCB). Single to multiple chips interconnects can be interconnected provided using the technique disclosed in this invention. The packaged chip includes semiconductor die and its package based on the ball-grid array or chip-scale-package. The O-E board includes the optoelectronics components and multiple electrical contacts on both sides of the O-E substrate. The waveguide board includes the electrical conductor transferring the signal from O-E board to PCB and the flex optical waveguide easily stackable onto the PCB to guide optical signal from one chip-to-other chip. Alternatively, the electrode can be directly connected to the PCB instead of including in the waveguide board. The chip-to-chip interconnections system is pin-free and compatible with the PCB. The main advantages of this invention are to use the packaged chip for interconnection and the conventional PCB technology can be used for low speed electrical signal connection. Also, the part of the heat from the packaged chip can be transmitted to the PCB through the conductors, so that complex cooling system can be avoided.

Abstract translation: 提供了一种光电子芯片到芯片互连系统，包括至少一个要连接在印刷电路板上的封装芯片与至少一个其它封装芯片，光电（OE）转换平均值，波导板和 （PCB）。 可以使用本发明公开的技术将单芯片至多片芯片互连互连。 封装芯片包括基于球栅阵列或芯片级封装的半导体管芯及其封装。 O-E板包括O-E基板两侧的光电子元件和多个电触点。 波导板包括将信号从O-E板传输到PCB的电导体，并且柔性光波导容易地堆叠到PCB上以引导来自一个芯片到另一个芯片的光信号。 或者，电极可以直接连接到PCB，而不是包括在波导板中。 芯片到芯片互连系统是无引脚的，与PCB兼容。 本发明的主要优点是使用封装芯片进行互连，并且传统的PCB技术可用于低速电信号连接。 此外，来自封装芯片的部分热量可以通过导体传输到PCB，从而可以避免复杂的冷却系统。

公开(公告)号：US08299594B2

公开(公告)日：2012-10-30

申请号：US12696185

申请日：2010-01-29

Applicant: Daniel Michaels ,  William E. Boyd

Inventor： Daniel Michaels ,  William E. Boyd

IPC: H01L23/02

CPC classification number: H05K1/147 ,  H01L25/105 ,  H01L2225/0652 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/144 ,  H05K3/3405 ,  H05K3/403 ,  H05K2201/0397 ,  H05K2201/09181 ,  H05K2201/10515 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A multilayer module comprised of stacked IC package layers is disclosed. A plurality of layers preferably having ball grid array I/O are stacked and interconnected using one or more interposer layers for the routing of electronic signals to appropriate locations in the module through angularly depending leads. The stack is further comprised of an interface PCB for the routing of electronics signals to and from the layers in the module and for connection to an external circuit.

Abstract translation: 公开了由堆叠的IC封装层组成的多层模块。 优选地具有球栅阵列I / O的多个层被堆叠并且使用一个或多个插入层相互连接，用于通过角度依赖的引线将电子信号路由到模块中的适当位置。 该堆叠还包括用于将电子信号路由到模块中的层和从模块中的层路由并用于连接到外部电路的接口PCB。

公开(公告)号：US20120262875A1

公开(公告)日：2012-10-18

申请号：US13163502

申请日：2011-06-17

Applicant: Morgan Johnson ,  Frederick G. Weiss

Inventor： Morgan Johnson ,  Frederick G. Weiss

IPC: G06F1/16 ,  G06F1/20

CPC classification number: G06F13/16 ,  G06F1/32 ,  G06F13/4068 ,  G11C5/04 ,  H01L23/32 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K1/147 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/095 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10522 ,  Y02D10/151 ,  Y10T29/4913 ,  H01L2924/00

Abstract: An interposer substrate includes an array of interconnects in the interposer substrate, the array of connectors arranged in accordance with an array of interconnects for a processor on a circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one connector in the array of interconnects, the conductive trace arranged parallel to the interposer substrate such that no electrical connection exists between the connector in the interposer substrate and a corresponding one of the interconnects for the processor on the circuit substrate, and at least one peripheral circuit residing on the interposer substrate in electrical connection with the conductive trace.

Abstract translation: 插入器衬底包括插入器衬底中的互连阵列，所述连接器阵列根据用于电路衬底上的处理器的互连阵列布置，所述插入器衬底中的至少一个导电迹线与至少一个连接器 所述互连阵列，所述导电迹线平行于所述插入器基板布置，使得在所述插入器基板中的所述连接器与所述电路基板上的所述处理器的相应的一个互连件之间不存在电连接;以及至少一个外围电路， 所述插入器衬底与所述导电迹线电连接。

公开(公告)号：US08289675B2

公开(公告)日：2012-10-16

申请号：US12616533

申请日：2009-11-11

Applicant: Daniel Devoe ,  Alan Devoe ,  Lambert Devoe

Inventor： Daniel Devoe ,  Alan Devoe ,  Lambert Devoe

IPC: H01G4/228

CPC classification number: H01G4/232 ,  H01G4/30 ,  H01G4/38 ,  H05K1/0231 ,  H05K1/181 ,  H05K3/3421 ,  H05K2201/10515 ,  H05K2201/10537 ,  H05K2201/10636 ,  H05K2201/10946 ,  Y02P70/611

Abstract: A capacitor device mountable on a plane of a substrate includes an electrically conductive bottom plate adapted to be mounted substantially parallel to, and in electrical contact at the plane of the substrate and a first multilayer capacitor having substantially parallel first and second electrode plates oriented substantially perpendicular to the bottom plate with the first electrode plates being electrically connected to the bottom plate. An electrically conductive top lead frame overlaps with, and is electrically isolated from, the bottom plate. The top lead frame electrically connected to the second electrode plates and adapted to be electrically connected at the plane of the substrate. The bottom lead frame may have a corrugated shape, where the corrugated shape provides compliance between the first multilayer capacitor and the substrate. A portion of the top lead frame may contact at least a portion of a side of the first multilayer capacitor.

Abstract translation: 可安装在基板的平面上的电容器装置包括导电底板，其适于基本平行于基板平行并且与基板平面电接触;以及第一多层电容器，其具有基本上平行的第一和第二电极板， 到底板，其中第一电极板电连接到底板。 导电顶部引线框架与底板重叠并与底板电隔离。 顶引线框架电连接到第二电极板并且适于在基板的平面处电连接。 底部引线框架可以具有波纹形状，其中波纹形状提供了第一层叠电容器和基板之间的柔顺性。 顶部引线框架的一部分可以接触第一层叠电容器的一侧的至少一部分。

公开(公告)号：US20120257321A1

公开(公告)日：2012-10-11

申请号：US13172836

申请日：2011-06-30

Applicant: CHUN-AN LAI

Inventor： CHUN-AN LAI

IPC: H01G4/002

CPC classification number: H01G2/06 ,  H01G4/30 ,  H01G4/38 ,  H01G9/14 ,  H01G11/12 ,  H05K1/181 ,  H05K3/301 ,  H05K2201/10015 ,  H05K2201/10515 ,  H05K2203/167 ,  Y02E60/13 ,  Y02P70/611

Abstract: A capacitor includes a main body, a first seat, and a second seat. The main body includes a first end surface and a second end surface opposite to the first end surface. Two first pins extend upward from the first end surface. Two second pins extend downward from the second end surface. The first pins electrically connect the second pins. The first seat includes a first substrate and two first pads, the first seat is positioned on the second end surface of the main body and the first pads are electrically connected to the second pins. The second seat includes a second substrate and two second pads, the second seat is positioned on the first end surface of the main body and the second pads are electrically connected to the first pins.

Abstract translation: 电容器包括主体，第一座和第二座。 主体包括第一端面和与第一端面相对的第二端面。 两个第一销从第一端面向上延伸。 两个第二销从第二端面向下延伸。 第一个引脚电连接第二个引脚。 第一座椅包括第一衬底和两个第一衬垫，第一座椅位于主体的第二端面上，并且第一衬垫电连接到第二插脚。 第二座椅包括第二衬底和两个第二衬垫，第二座椅位于主体的第一端面上，第二衬垫电连接到第一插脚。