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    ELECTRONIC APPARATUS AND SUBSTRATE MOUNTING METHOD
    81.
    发明申请
    ELECTRONIC APPARATUS AND SUBSTRATE MOUNTING METHOD 审中-公开
    电子装置和基板安装方法

    公开(公告)号：US20090168386A1

    公开(公告)日：2009-07-02

    申请号：US12248748

    申请日：2008-10-09

    Applicant: Daigo Suzuki ,  Akihiko Happoya

    Inventor： Daigo Suzuki ,  Akihiko Happoya

    IPC: H05K7/02 ,  H01L21/52

    CPC classification number: H05K9/003 ,  H01L23/552 ,  H01L25/165 ,  H01L2924/1617 ,  H01L2924/3011 ,  H05K1/0218 ,  H05K1/141 ,  H05K1/181 ,  H05K2201/10378 ,  H05K2201/2018 ,  H05K2201/2036 ,  H05K2203/1572

    Abstract: According to one embodiment, an electronic apparatus comprises a frame with a hollow portion formed inside thereof, a shield coating applied to the inner surface of the frame, a plurality of connection terminals having lead portions provided on the outside surface of the frame, and a module substrate which mounts circuit components on the front and rear surfaces thereof and which is placed on the frame in a state where at least the rear side circuit components are housed in the hollow portion with the circuit components on the front and rear surfaces connected to the connection terminals.

    Abstract translation: 根据一个实施例，一种电子设备包括：在其内部形成有中空部分的框架，施加到框架内表面的屏蔽涂层;多个连接端子，其具有设置在框架的外表面上的引线部分;以及 模块基板，其在其前表面和后表面上安装电路部件，并且在至少后侧电路部件容纳在中空部分中的状态下放置在框架上，其中电路部件在前后表面连接到中空部分 连接端子。

    High capacity thin module system and method
    82.
    发明授权
    High capacity thin module system and method 有权
    大容量薄模块系统及方法

    公开(公告)号：US07522425B2

    公开(公告)日：2009-04-21

    申请号：US11869687

    申请日：2007-10-09

    Applicant: Paul Goodwin

    Inventor： Paul Goodwin

    IPC: H05K1/00

    CPC classification number: G11C5/04 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/118 ,  H05K1/181 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2203/1572 ,  H01L2224/0401

    Abstract: Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers. Other embodiments may stagger or offset the ICs or include greater numbers of ICs.

    Abstract translation: 多个DIMM电路或实例被呈现在单个模块中。 在一些实施例中，存储器集成电路（优选CSP）和伴随的AMB或伴随的存储器寄存器被布置在柔性电路的每一侧的两个场中的两个等级中。 柔性电路具有沿着一侧设置的扩展触点。 柔性电路围绕支撑衬底或板设置，以在构造的模块的每一侧上放置一个完整的DIMM电路或实例化。 在替代但也是优选实施例中，最靠近基板的柔性电路侧的IC至少部分地设置在优选实施例中在基板中的窗口，凹部或切口区域中。 其他实施例可以仅填充柔性电路的一侧，或者可以仅移除足够的衬底材料以减少但不消除整个衬底对整体轮廓的贡献。 柔性电路可以表现出一个或两个或更多个导电层，并且可以具有分层结构的变化或具有分裂层。 其他实施例可能错开或偏移IC或包括更多数量的IC。

    Circuit Device
    83.
    发明申请
    Circuit Device 有权
    电路设备

    公开(公告)号：US20090091899A1

    公开(公告)日：2009-04-09

    申请号：US12237650

    申请日：2008-09-25

    Applicant: Hidefumi Saito

    Inventor： Hidefumi Saito

    IPC: H05K5/00

    CPC classification number: H05K3/284 ,  H01L23/24 ,  H01L23/3735 ,  H01L23/49811 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/165 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/056 ,  H05K3/0061 ,  H05K2201/10409 ,  H05K2201/10946 ,  H05K2201/2018 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

    Abstract: The present invention provides a circuit device in which warpage of a case member is prevented. The circuit device of the present invention includes: a circuit board having on an upper surface thereof a built-in hybrid integrated circuit constituted by a conductive pattern and a circuit element; a case member including four side wall parts forming a frame-like shape and being in contact with the circuit board so as to form on the upper surface of the circuit board a space in which the circuit element is sealed; and a lead being fixed to a pad composed of the conductive pattern and extending to the outside. The circuit device of the present invention is further provided with a supporting part arranged at a corner of the case member so as to make continuous inner walls of the respective side wall parts with each other.

    Abstract translation: 本发明提供了一种电路装置，其中防止了壳体构件的翘曲。 本发明的电路装置包括：电路板，其上表面具有由导电图案和电路元件构成的内置混合集成电路; 壳体构件，包括形成框状形状并与电路板接触的四个侧壁部，以在电路板的上表面上形成电路元件被密封的空间; 并且引线固定到由导电图案组成并延伸到外部的焊盘。 本发明的电路装置还具有设置在壳体的角部的支撑部，以使各个侧壁部的连续的内壁彼此成一体。

    Buffered thin module system and method
    85.
    发明授权
    Buffered thin module system and method 有权
    缓冲薄模块系统和方法

    公开(公告)号：US07511968B2

    公开(公告)日：2009-03-31

    申请号：US11007551

    申请日：2004-12-08

    Applicant: Paul Goodwin

    Inventor： Paul Goodwin

    IPC: H05K1/11

    CPC classification number: G11C5/04 ,  H01L23/34 ,  H01L23/36 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/118 ,  H05K1/181 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2203/1572 ,  H01L2224/0401

    Abstract: Multiple fully buffered DIMM circuits or instantiations are presented in a single module. In a preferred embodiment, memory integrated circuits (preferably CSPs) and accompanying AMBs are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete FB-DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers. Other embodiments may stagger or offset the ICs or include greater numbers of ICs.

    Abstract translation: 多个完全缓冲的DIMM电路或实例被呈现在单个模块中。 在优选实施例中，存储器集成电路（优选CSP）和伴随的AMB被布置在柔性电路的每一侧的两个场中的两个等级中。 柔性电路具有沿着一侧设置的扩展触点。 柔性电路围绕支撑衬底或板设置，以在构造的模块的每一侧上放置一个完整的FB-DIMM电路或实例化。 在替代但也是优选实施例中，最靠近基板的柔性电路侧的IC至少部分地设置在优选实施例中在基板中的窗口，凹部或切口区域中。 其他实施例可以仅填充柔性电路的一侧，或者可以仅移除足够的衬底材料以减少但不消除整个衬底对整体轮廓的贡献。 柔性电路可以表现出一个或两个或更多个导电层，并且可能具有分层结构的变化或具有分裂层。 其他实施例可能错开或偏移IC或包括更多数量的IC。

    PRINTED CIRCUIT BOARD ASSEMBLY
    86.
    发明申请
    PRINTED CIRCUIT BOARD ASSEMBLY 审中-公开
    印刷电路板组装

    公开(公告)号：US20090034218A1

    公开(公告)日：2009-02-05

    申请号：US11946481

    申请日：2007-11-28

    Applicant: CHIH-KAI HU

    Inventor： CHIH-KAI HU

    IPC: H01R9/00

    CPC classification number: H05K1/141 ,  H05K1/0218 ,  H05K2201/10371 ,  H05K2201/10409 ,  H05K2201/2018

    Abstract: A printed circuit board assembly (20) is provided. The printed circuit board assembly includes a main printed circuit board (22), an accessorial printed circuit board (26), and a frame (24). The main printed circuit board includes at least one electronic component (222). The frame is secured to the main printed circuit board. The accessorial printed circuit board is attached to the main printed circuit board. The accessorial printed circuit board includes a shielding area (262). The shielding area is configured for engaging with the frame, whereby the shielding area and the frame cooperatively shield the at least one electronic component therein.

    Abstract translation: 提供一种印刷电路板组件（20）。 印刷电路板组件包括主印刷电路板（22），辅助印刷电路板（26）和框架（24）。 主印刷电路板包括至少一个电子部件（222）。 框架固定在主印刷电路板上。 辅助印刷电路板连接到主印刷电路板。 辅助印刷电路板包括屏蔽区域（262）。 屏蔽区域被配置为与框架接合，由此屏蔽区域和框架协同地屏蔽其中的至少一个电子部件。

    Substrate Joining Member and Three-Dimensional Structure Using the Same
    87.
    发明申请
    Substrate Joining Member and Three-Dimensional Structure Using the Same 有权
    基板连接构件和三维结构使用它

    公开(公告)号：US20090009979A1

    公开(公告)日：2009-01-08

    申请号：US12280434

    申请日：2007-04-23

    Applicant: Masato Mori ,  Daido Komyoji ,  Koichi Nagai ,  Yoshihiko Yagi

    Inventor： Masato Mori ,  Daido Komyoji ,  Koichi Nagai ,  Yoshihiko Yagi

    IPC: H05K1/14 ,  H01R12/00

    CPC classification number: H05K1/144 ,  B23K1/0016 ,  B23K2101/42 ,  H05K3/368 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2201/2018 ,  H05K2203/1572

    Abstract: Three-dimensional structure (40) of the present invention includes first module board (28), second module board (37), and substrate joining member (10) that unifies board (28) and board (37) into one body, thereby electrically connecting these two elements together. The unification is done by molding the outer wall of housing (12) of substrate joining member (10) with resin (29). Substrate joining member (10) used in the three-dimensional structure (40) includes multiple lead terminals (14) made of conductive material, and a frame-shaped and insulating housing (12) to which frame the lead terminals (14) are fixed vertically in a predetermined array. Housing (12) includes projections (18) on at least two outer wall faces of its frame shape.

    Abstract translation: 本发明的三维结构（40）包括将板（28）和板（37）一体化成一体的第一模块板（28），第二模块板（37）和基板接合构件（10），由此电 将这两个元素连接在一起。 通过用树脂（29）将衬底接合构件（10）的壳体（12）的外壁模制成一体。 在三维结构（40）中使用的基板接合构件（10）包括由导电材料制成的多个引线端子（14）和框架形绝缘壳体（12），引线端子（14）固定到框架形绝缘壳体 垂直于预定阵列。 壳体（12）在其框架形状的至少两个外壁面上包括突起（18）。

    Hybrid Integrated Circuit Device and Method for Manufacturing Same
    88.
    发明申请
    Hybrid Integrated Circuit Device and Method for Manufacturing Same 有权
    混合集成电路装置及其制造方法

    公开(公告)号：US20080278920A1

    公开(公告)日：2008-11-13

    申请号：US12083039

    申请日：2006-10-02

    Applicant: Seitaro Mizuhara ,  Naoya Tanaka

    Inventor： Seitaro Mizuhara ,  Naoya Tanaka

    IPC: H05K7/00 ,  H05K3/30

    CPC classification number: H05K1/141 ,  H01L23/49805 ,  H01L23/49811 ,  H01L25/16 ,  H01L2924/0002 ,  H05K1/145 ,  H05K3/0052 ,  H05K3/3442 ,  H05K3/368 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/10378 ,  H05K2201/2018 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: A hybrid integrated circuit device includes: an insulating substrate (1) having a lower surface formed with wiring patterns including ends arranged along ends of the lower surface at a predetermined pitch (P); electronic components (3) mounted on the surfaces of the insulating substrate to be connected to the wiring patterns; a pair of insulating legs (2) arranged at the ends of the lower surface of the substrate (1), each insulating leg extending in parallel to the lower surface of the substrate (1); and a plurality of terminal electrodes (5) formed on each leg at the pitch and extending perpendicularly to the substrate, where the plurality of terminal electrodes are connected to the wiring patterns on the lower surface of the substrate (1). Each leg has a surface bonded to the substrate and formed with electrode films connected to the terminal electrodes. Each leg is fixed to the substrate by attaching the terminal electrodes to the wiring patterns on the lower surface of the substrate (1) by soldering or by an electroconductive paste.

    Abstract translation: 一种混合集成电路装置，包括：绝缘基板（1），其具有形成有布线图案的下表面，所述布线图案包括以预定间距（P）沿所述下表面的端部布置的端部; 电子部件（3），安装在所述绝缘基板的与所述布线图形连接的表面上; 布置在基板（1）的下表面的端部处的一对绝缘支脚（2），每个绝缘支脚平行于基板（1）的下表面延伸; 以及多个端子电极（5），其以间距形成在每个支脚上并垂直于基板延伸，其中多个端子电极连接到基板（1）的下表面上的布线图案。 每个腿部具有与基板结合的表面，并且形成有连接到端子电极的电极膜。 通过焊接或通过导电浆将端子电极附接到基板（1）的下表面上的布线图案，将每个支脚固定到基板。

    Carrier structure stacking system and method
    90.
    发明授权
    Carrier structure stacking system and method 有权
    载体结构堆垛系统及方法

    公开(公告)号：US07446403B2

    公开(公告)日：2008-11-04

    申请号：US11452531

    申请日：2006-06-14

    Applicant: Julian Partridge

    Inventor： Julian Partridge

    IPC: H01L23/02 ,  H05K7/00 ,  H01R12/04

    CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K3/429 ,  H05K2201/09481 ,  H05K2201/0959 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/2018 ,  H01L2924/00

    Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits.

    Abstract translation: 本发明提供了一种系统和方法，用于选择性地堆叠和互连带引线的封装集成电路器件，其具有上IC的引线的脚与下IC的引线的上肩之间的连接，而实现堆叠相关的堆叠内的导电性转换 组成IC之间的连接在沿着堆叠的引导侧定向的多层插入件或载体结构中实现，其中选定的导电转移与其它选定的导电转换电互连。

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