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    ULTRA-THIN PACKAGE STRUCTURE FOR INTEGRATED CIRCUIT HAVING SENSING FUNCTION AND METHOD FORMING THE SAME
    1.
    发明申请
    ULTRA-THIN PACKAGE STRUCTURE FOR INTEGRATED CIRCUIT HAVING SENSING FUNCTION AND METHOD FORMING THE SAME 有权

    公开(公告)号：US20210104563A1

    公开(公告)日：2021-04-08

    申请号：US16590463

    申请日：2019-10-02

    Applicant: SunASIC Technologies, Inc.

    Inventor： Chi-Chou LIN ,  Zheng Ping HE

    IPC: H01L27/146 ,  H01L23/31 ,  H01L23/66 ,  H01L21/48 ,  H01L23/29 ,  H01L25/16 ,  H01L23/13

    Abstract: An ultra-thin package structure for an integrated circuit having sensing functions is disclosed. It includes: a first substrate layer, having a first top side and a first bottom side, wherein a plurality of conductive traces are formed on the first top side and the first bottom side; an integrated circuit, having at least one gold-plated die pad on the top side thereof, wherein the at least one gold-plated die pad is connected to the corresponding conductive trace on the first bottom side of the first substrate layer by SMT; a second substrate layer, having a second top side and a second bottom side, wherein a plurality of conductive traces are formed on the second bottom side, and some portions of the conductive traces are covered by solder mask while other portions are exposed externally; and a filling material layer, formed between the first and the second substrate layer with the integrated circuit therebetween.

    NOISE REDUCED CAPACITIVE FINGERPRINT SENSOR AND CAPACITIVE SENSING UNIT INCLUDED THEREIN
    2.
    发明申请
    NOISE REDUCED CAPACITIVE FINGERPRINT SENSOR AND CAPACITIVE SENSING UNIT INCLUDED THEREIN 审中-公开

    公开(公告)号：US20180173919A1

    公开(公告)日：2018-06-21

    申请号：US15381182

    申请日：2016-12-16

    Applicant: SunASIC Technologies, Inc.

    Inventor： Chi Chou LIN ,  Zheng Ping HE

    IPC: G06K9/00 ,  H04N5/365 ,  H03K17/96 ,  H01L27/06

    CPC classification number: G06K9/0002 ,  H01L27/0629 ,  H03K17/9622 ,  H04N5/365

    Abstract: A capacitive fingerprint sensor which includes capacitive sensing units is disclosed. Each of the capacitive sensing unit includes a sensing electrode; a first switch; a voltage follower; and a reference capacitor. The voltage follower includes an adjustable current source, for providing at least two distinct current levels; and a MOS transistor. The MOS transistor includes a source node, connected to ground via the adjustable current source and serves as an output node of the voltage follower; a gate node, connected to the sensing electrode and serves as an input node of the voltage follower; a drain node, connected to a power source, for providing power to the voltage follower; and a bulk node, connected to the source node.

    METHOD FOR MOUNTING CHIP ON PRINTED CIRCUIT BOARD
    5.
    发明申请
    METHOD FOR MOUNTING CHIP ON PRINTED CIRCUIT BOARD 有权
    印刷电路板上安装芯片的方法

    公开(公告)号：US20160079289A1

    公开(公告)日：2016-03-17

    申请号：US14488814

    申请日：2014-09-17

    Applicant: SUNASIC TECHNOLOGIES, INC.

    Inventor： Chi-Chou LIN ,  Zheng-Ping HE

    IPC: H01L27/146

    CPC classification number: H01L27/1469 ,  H01L21/4857 ,  H01L21/4867 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L27/146 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/484 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153

    Abstract: A method for mounting a chip on a printed circuit board (PCB) is disclosed. The method includes the steps of: providing a chip having a plurality of bonding pads and a PCB having a recess portion and a plurality of connectors; gluing the recess portion; placing the chip into the recess portion; and forming circuit patterns linking associated bonding pad and connector. A bottom of the recess portion is substantially flat and a shape of the recess portion is similar to that of the chip but large enough so that the chip can be fixed in the recess portion after being glued.

    Abstract translation: 公开了一种将芯片安装在印刷电路板（PCB）上的方法。 该方法包括以下步骤：提供具有多个接合焊盘的芯片和具有凹部和多个连接器的PCB; 胶合所述凹部; 将所述芯片放置在所述凹部中; 以及形成连接相关联的焊盘和连接器的电路图案。 凹部的底部基本上是平坦的，并且凹部的形状与芯片的形状相似但足够大，使得芯片可以在胶合之后固定在凹部中。

    MULTI-FUNCTION IDENTIFICATION SYSTEM AND OPERATION METHOD THEREOF
    6.
    发明申请
    MULTI-FUNCTION IDENTIFICATION SYSTEM AND OPERATION METHOD THEREOF 有权
    多功能识别系统及其操作方法

    公开(公告)号：US20150127951A1

    公开(公告)日：2015-05-07

    申请号：US14071760

    申请日：2013-11-05

    Applicant: SunASIC Technologies, Inc.

    Inventor： Chi-Chou LIN

    IPC: G06F21/32

    CPC classification number: G06F21/32 ,  G06F21/35 ,  G06F21/44 ,  G07C2009/00984

    Abstract: A multi-function identification system is described in the present invention. The system includes an appliance and a number of keys. Under a registration process, the system allows multiple appliances to be controlled by a single key or an appliance can be controlled by different keys. The system can also allow users to set specified actions to be conducted after identification processes are completed. That satisfies requirements of a multi-function identification. Meanwhile, the key is a plug-and play and on-the-go product. It is desired that the key is a host used for other purpose.

    Abstract translation: 在本发明中描述了一种多功能识别系统。 该系统包括一个设备和多个按键。 在注册过程中，系统允许通过单个密钥控制多个设备，或者可以通过不同的密钥来控制设备。 系统还可以允许用户在识别过程完成后设置指定的操作。 满足多功能识别的要求。 同时，关键是即插即用产品。 希望密钥是用于其他目的的主机。

    COMPOUND AND SECURABLE KEY
    7.
    发明申请
    COMPOUND AND SECURABLE KEY 有权
    化合物和可固化的键

    公开(公告)号：US20150123764A1

    公开(公告)日：2015-05-07

    申请号：US14071737

    申请日：2013-11-05

    Applicant: SunASIC Technologies, Inc.

    Inventor： Chi-Chou LIN

    IPC: G07C9/00

    CPC classification number: G07C9/00563 ,  G07C9/00944 ,  G07C2009/00095

    Abstract: A compound and securable key is disclosed in the present invention. It includes a printed circuit board, a fingerprint sensor, a micro control unit, and a housing. The present invention provides a key structure with combination of a physical key patterns and biometrics for identification. The key is convenient to carry, difficult to duplicate. It is also has advantages such as low cost, easy use, and compact size of biometric module. The invention enhances security of keys.

    Abstract translation: 在本发明中公开了复合和安全密钥。 它包括印刷电路板，指纹传感器，微控制单元和壳体。 本发明提供了一种结合物理密钥图案和用于识别的生物特征的密钥结构。 钥匙携带方便，难以复制。 它还具有生物识别模块成本低，使用方便，体积小巧等优点。 本发明提高了密钥的安全性。

    BIOMETRIC SECURITY DEVICE
    8.
    发明申请
    BIOMETRIC SECURITY DEVICE 审中-公开

    公开(公告)号：US20190311097A1

    公开(公告)日：2019-10-10

    申请号：US15947956

    申请日：2018-04-09

    Applicant: SunASIC Technologies, Inc.

    Inventor： Chi Chou LIN ,  Zheng Ping HE

    IPC: G06F21/32 ,  G06F17/30 ,  G07C9/00 ,  G06F21/62

    Abstract: A biometric security device for digital key storing is disclosed. The biometric security device includes a biometric information fetching module and a processing module. The processing module has a nonvolatile storage unit and a processing unit. The nonvolatile storage unit includes a secure storage unit and a general storage unit. The biometric security device with a secure electronic key designed for storing secret data utilizes both TrustZone™ technology (or similar technology) and biometric authentication. Thus, it can provide the flexibility for multiple users or applications to use the biometric security device or any equipment the biometric security device mounted in without compromising the safeguard of the data stored therein.

    Silicon wafer having colored top side
    9.
    发明授权
    Silicon wafer having colored top side 有权

    公开(公告)号：US10168450B2

    公开(公告)日：2019-01-01

    申请号：US14141717

    申请日：2013-12-27

    Applicant: SunASIC Technologies, Inc.

    Inventor： Chi-Chou Lin ,  Zheng-Ping He

    IPC: H01L23/544 ,  H01L21/76 ,  G02B1/00 ,  G02B5/18 ,  G02B5/20

    Abstract: A silicon wafer having colored top side is disclosed in the present invention. The silicon wafer includes: a wafer; a first semi-conductor layer, formed on at least a portion of a top side of the wafer, having periodical structures to form a grating pattern, and a second semi-conductor layer, formed on the first semi-conductor layer with a bottom side substantially fully contacted with the periodical structures. The first semi-conductor layer and the second semi-conductor layer form a photonic crystal layer and work to reflect a predetermined wavelength range of incident visible light beams. The present invention provides a silicon wafer which can reflect specified color(s) from the surface facing external light beams. Therefore, dies from cutting the silicon wafer with functions to interact with external environment rather than packaged can have advantages to show some specified logo or trademark.

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