中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

200 records (took 0.021 seconds)

    A METHOD AND SYSTEM FOR DISCRIMINATING DEFECTS PRESENT ON A FRONTSIDE FROM DEFECTS PRESENT ON A BACKSIDE OF A TRANSPARENT SUBSTRATE
    1.
    发明申请
    A METHOD AND SYSTEM FOR DISCRIMINATING DEFECTS PRESENT ON A FRONTSIDE FROM DEFECTS PRESENT ON A BACKSIDE OF A TRANSPARENT SUBSTRATE 有权

    公开(公告)号：US20250052692A1

    公开(公告)日：2025-02-13

    申请号：US18722087

    申请日：2022-11-17

    Applicant: Unity Semiconductor ,  Unity Semiconductor GmbH

    Inventor： Alexey Butkevich ,  Jean Boulanger

    IPC: G01N21/958 ,  G01N21/47

    Abstract: Method for discriminating defects present on a frontside of a transparent substrate from defects present on a backside of the substrate comprises disposing the substrate in an inspection system in which first and a second light beams intersect at a measurement spot on the frontside of the substrate. Relative movement of the substrate and measurement spot is controlled such that a reference plane is kept tangential to the measurement path. A first pattern is identified in a measurement signal, the first pattern corresponding to light scattered by a particle on the backside of the substrate and presenting two intensity peaks separated from each other by a determined separation interval corresponding to the time necessary for the defect to be moved over the distance separating two illumination spots on the backside of the substrate.

    Method and a system for characterizing structures through a substrate
    3.
    发明授权
    Method and a system for characterizing structures through a substrate 有权

    公开(公告)号：US12123698B1

    公开(公告)日：2024-10-22

    申请号：US18739436

    申请日：2024-06-11

    Applicant: UNITY SEMICONDUCTOR

    Inventor： Alain Courteville ,  Michael Schöbitz ,  Wolfgang Alexander Iff

    IPC: G01B11/02 ,  G01B11/26

    CPC classification number: G01B11/02 ,  G01B11/26 ,  G01B2210/56

    Abstract: A method for characterizing a structure etched in a first substrate surface, the structure extending along a longitudinal direction, z, into the substrate, the method implemented by a system including a light source emitting an illumination beam with a wavelength transmitted through the substrate, and an imaging device positioned to face a second substrate surface opposite the first surface, the method including illuminating at least one structure with the illumination beam, subsequently positioning an object plane of the imaging device at at least two different longitudinal positions; acquiring at least one image of the structure at each of the longitudinal positions, the images being acquired through the substrate; measuring data relating to a lateral dimension of the structure from each acquired image at each of the longitudinal positions; and determining longitudinal data relating to a longitudinal shape of the structure from the lateral data of at least two longitudinal positions.

    Vertical cross-point arrays for ultra-high-density memory applications
    7.
    发明授权
    Vertical cross-point arrays for ultra-high-density memory applications 有权

    公开(公告)号：US10790334B2

    公开(公告)日：2020-09-29

    申请号：US15633050

    申请日：2017-06-26

    Applicant: Unity Semiconductor Corporation

    Inventor： Bruce Lynn Bateman

    IPC: H01L45/00 ,  H01L27/24

    Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

    Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements
    8.
    发明授权
    Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements 有权

    公开(公告)号：US10788993B2

    公开(公告)日：2020-09-29

    申请号：US16811401

    申请日：2020-03-06

    Applicant: Unity Semiconductor Corporation

    Inventor： Chang Hua Siau

    IPC: G11C11/00 ,  G06F3/06 ,  G11C11/419 ,  G11C13/00 ,  G11C5/06 ,  G11C8/08

    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

Patent Agency Ranking