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公开(公告)号：US08932476B2
公开(公告)日：2015-01-13
申请号：US13762117
申请日：2013-02-07
Applicant: Infineon Technologies AG
Inventor： Thomas Kunstmann , Stefan Willkofer , Anja Gissibl , Johann Strasser , Matthias Mueller , Eva-Maria Hess
CPC classification number: C23F1/02 , C23F1/08 , C23F1/18 , H01L21/32134 , H01L23/53228 , H01L2924/0002 , H01L2924/00
Abstract: Apparatuses and methods are provided where porous metal is deposited on a substrate, a mask is provided on the porous metal and then an etching is performed.
Abstract translation: 提供了将多孔金属沉积在基底上的设备和方法，在多孔金属上提供掩模，然后进行蚀刻。
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公开(公告)号：US09355984B2
公开(公告)日：2016-05-31
申请号：US13944927
申请日：2013-07-18
Applicant: Infineon Technologies AG
Inventor： Irmgard Escher-Poeppel , Eduard Knauer , Thomas Kunstmann , Peter Scherl , Raimund Foerg
IPC: H01L23/00 , H01L23/373
CPC classification number: H01L24/29 , H01L23/3736 , H01L24/27 , H01L24/743 , H01L24/83 , H01L24/94 , H01L2224/27332 , H01L2224/27848 , H01L2224/29247 , H01L2224/29647 , H01L2224/32145 , H01L2224/32245 , H01L2224/83011 , H01L2224/83065 , H01L2224/83193 , H01L2224/83203 , H01L2224/8384 , H01L2224/85547 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/12042 , H01L2924/15747 , H01L2924/181 , H01L2924/01001 , H01L2924/20106 , H01L2924/00
Abstract: An embodiment method for fabricating electronic devices having two components connected by a metal layer includes applying a metal layer to each component and connecting the metal layers such that a single metal layer is formed.
Abstract translation: 用于制造具有通过金属层连接的两个部件的电子器件的实施例方法包括将金属层施加到每个部件并连接金属层，使得形成单个金属层。
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Patent Agency Ranking
公开(公告)号：US20140242374A1
公开(公告)日：2014-08-28
申请号：US13774624
申请日：2013-02-22
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Johann Strasser , Thomas Kunstmann , Manfred Frank , Werner Robl , Maximilian Krug , Simon Faiss , Matthias Mueller
CPC classification number: H01L23/14 , B05D7/52 , B32B3/26 , C23C18/1644 , C23C18/1651 , C23C18/32 , C23C18/50 , C25D7/12 , C25D7/123 , H01L23/3733 , H01L23/49866 , H01L23/53238 , H01L2924/0002 , Y10T428/249956 , Y10T428/249957 , Y10T428/24997 , H01L2924/00
Abstract: Various methods, apparatuses and devices relate to porous metal layers on a substrate which are three-dimensionally coated. In one embodiment, a porous metal layer is deposited over a substrate. The porous metal layer can be three-dimensionally coated with a coating material.
Abstract translation: 各种方法，装置和装置涉及三维涂覆在基底上的多孔金属层。 在一个实施例中，多孔金属层沉积在衬底上。 多孔金属层可以用涂料三维涂覆。
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4.发明授权公开(公告)号：US08815743B2
公开(公告)日：2014-08-26
申请号：US13830185
申请日：2013-03-14
Applicant: Infineon Technologies AG
Inventor： Albert Birner , Uwe Hoeckele , Thomas Kunstmann , Uwe Seidel
IPC: H01L21/311
CPC classification number: H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/05571 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2924/00014 , H01L2924/0002 , H01L2924/01019 , H01L2924/01068 , H01L2924/01079 , H01L2924/00012 , H01L2224/05552
Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.
Abstract translation: 描述了在形成半导体部件时通过衬底通孔形成的结构和方法。 在一个实施例中，本发明描述了一种通过用第一填充材料填充开口形成通孔基底通孔的方法，并且在第一填充材料上沉积第一绝缘层，第一绝缘层不被沉积在填充材料的侧壁上 所述开口，其中所述第一绝缘层的侧壁在所述开口上形成间隙。 该方法还包括通过使用第二绝缘层密封开口来形成空隙。
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公开(公告)号：US09362127B2
公开(公告)日：2016-06-07
申请号：US13948208
申请日：2013-07-23
Applicant: Infineon Technologies AG
Inventor： Michael Krenzer , Thomas Kunstmann , Eva-Maria Hess , Manfred Frank
IPC: H01L21/285 , H01L21/02 , H01L23/532
CPC classification number: H01L21/28506 , H01L21/02068 , H01L23/53214 , H01L23/53228 , H01L23/53242 , H01L2924/0002 , H01L2924/00
Abstract: A method for processing a workpiece may include: providing a workpiece including a first region and a second region; forming a porous metal layer over the first region and the second region; wherein the first region and the second region are configured such that an adhesive force between the second region and the porous metal layer is lower than an adhesive force between the first region and the porous metal layer.
Abstract translation: 一种用于处理工件的方法可以包括：提供包括第一区域和第二区域的工件; 在所述第一区域和所述第二区域上形成多孔金属层; 其中所述第一区域和所述第二区域被构造成使得所述第二区域和所述多孔金属层之间的粘合力低于所述第一区域和所述多孔金属层之间的粘合力。
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公开(公告)号：US20140217062A1
公开(公告)日：2014-08-07
申请号：US13762117
申请日：2013-02-07
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Thomas Kunstmann , Stefan Willkofer , Anja Gissibl , Johann Strasser , Matthias Mueller , Eva-Maria Hess
CPC classification number: C23F1/02 , C23F1/08 , C23F1/18 , H01L21/32134 , H01L23/53228 , H01L2924/0002 , H01L2924/00
Abstract: Apparatuses and methods are provided where porous metal is deposited on a substrate, a mask is provided on the porous metal and then an etching is performed.
Abstract translation: 提供了将多孔金属沉积在基底上的设备和方法，在多孔金属上提供掩模，然后进行蚀刻。
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7.发明申请Through Substrate Via Semiconductor Components And Methods of Formation Thereof 有权通过基板通过半导体元件及其形成方法公开(公告)号：US20130267093A1
公开(公告)日：2013-10-10
申请号：US13830185
申请日：2013-03-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Albert Birner , Uwe Hoeckele , Thomas Kunstmann , Uwe Seidel
IPC: H01L21/768
CPC classification number: H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/05571 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2924/00014 , H01L2924/0002 , H01L2924/01019 , H01L2924/01068 , H01L2924/01079 , H01L2924/00012 , H01L2224/05552
Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.
Abstract translation: 描述了在形成半导体部件时通过衬底通孔形成的结构和方法。 在一个实施例中，本发明描述了一种通过用第一填充材料填充开口形成通孔基底通孔的方法，并且在第一填充材料上沉积第一绝缘层，第一绝缘层未沉积在填充材料的侧壁上 所述开口，其中所述第一绝缘层的侧壁在所述开口上形成间隙。 该方法还包括通过使用第二绝缘层密封开口来形成空隙。
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