公开(公告)号：US09659899B2

公开(公告)日：2017-05-23

申请号：US14796759

申请日：2015-07-10

Applicant: INTEL CORPORATION

Inventor： Sandeep B. Sane ,  Shankar Ganapathysubramanian ,  Jorge Sanchez ,  Leonel R. Arana ,  Eric J. Li ,  Nitin A. Deshpande ,  Jiraporn Seangatith ,  Poh Chieh Benny Poon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/32 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/89 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/3213 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/73253 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/161 ,  H01L2924/16251 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014

Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.

公开(公告)号：US20150318258A1

公开(公告)日：2015-11-05

申请号：US14796759

申请日：2015-07-10

Applicant: INTEL CORPORATION

Inventor： SANDEEP B. SANE ,  Shankar Ganapathysubramanian ,  Jorge Sanchez ,  Leonel R. Arana ,  Eric J. Li ,  Nitin A. Deshpande ,  Jiraporn Seangatith ,  Poh Chieh Benny Poon

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/89 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/3213 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/73253 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/161 ,  H01L2924/16251 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014

Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.

Abstract translation: 控制模具翘曲，用于组装薄模具。 在一个示例中，半导体管芯具有背侧和与背面相对的前侧。 背面具有半导体衬底，并且前侧具有在前侧层上形成在半导体衬底上的部件。 在半导体管芯的背面形成有背面层，以在管芯被加热时抵抗管芯的翘曲，并且在管芯的前侧形成多个接触件以附着到衬底上。

公开(公告)号：US09258880B2

公开(公告)日：2016-02-09

申请号：US13987701

申请日：2013-08-22

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Vladimir Noveski ,  Sujit Sharan ,  Shankar Ganapathysubramanian

IPC: H05H1/02 ,  H05K1/02 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498 ,  H05K3/46 ,  H05K1/03 ,  H05K3/06 ,  H05K3/10 ,  H05K3/20 ,  H05K3/38

CPC classification number: H05K1/0201 ,  H01L21/4807 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/107 ,  H05K3/205 ,  H05K3/388 ,  H05K3/4617 ,  H05K3/4629 ,  H05K3/4647 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.