公开(公告)号：US20160332864A1

公开(公告)日：2016-11-17

申请号：US15147197

申请日：2016-05-05

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Antti IIHOLA ,  Altti TORKKELI ,  Ville-Pekka RYTKÖNEN ,  Matti LIUKKU

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0021 ,  B81B3/0094 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0136 ,  B81B2203/04 ,  B81C1/00357 ,  B81C2201/0112 ,  B81C2201/0132

Abstract: The present invention relates to a micromechanical device comprising a multi-layer micromechanical structure including only homogenous silicon material. The device layer comprises at least a rotor and at least two stators. At least some of the rotor and at least two stators are at least partially recessed to at least two different depths of recession from a first surface of the device layer and at least some of the rotor and at least two stators are at least partially recessed to at least two different depths of recession from a second surface of the device layer.

Abstract translation: 微机械装置技术领域本发明涉及包括仅包含均质硅材料的多层微机械结构的微机械装置。 装置层至少包括一个转子和至少两个定子。 转子和至少两个定子中的至少一些至少部分地凹陷到来自装置层的第一表面的至少两个不同的凹陷深度，并且至少一些转子和至少两个定子至少部分地凹入 与器件层的第二表面的至少两个不同的凹陷深度。

公开(公告)号：US20240116753A1

公开(公告)日：2024-04-11

申请号：US18483980

申请日：2023-10-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Antti IIHOLA ,  Jeanette LINDROOS

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B2207/095 ,  B81C2203/0118

Abstract: A method is provided for sealing and contacting a microelectromechanical device that includes a silicon device wafer with MEMS device structures and a cap wafer with an electrical circuit. The device wafer includes a sealing region and an interconnection region. Moreover, the cap wafer includes a corresponding sealing region and an interconnection region. Layers of eutectic metal alloy material are deposited on the sealing and the interconnection regions of the device wafer and the cap wafer. The cap wafer is bonded to the device wafer so that the interconnection region of the device wafer is aligned with the interconnection region of the cap wafer and the sealing region of the device wafer is aligned with the sealing region of the cap wafer.

公开(公告)号：US20160332872A1

公开(公告)日：2016-11-17

申请号：US15147233

申请日：2016-05-05

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Antti IIHOLA ,  Altti TORKKELI

IPC: B81C1/00

CPC classification number: B81C1/00595 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/033 ,  B81B2203/0136 ,  B81C1/00603 ,  G01C19/56 ,  G01C19/5733 ,  G01C19/5769

Abstract: A method for manufacturing a micromechanical device layer is performed on a device wafer comprising a single layer of homogenous material. The method comprises patterning a first mask on a first face of the device wafer, the first mask patterning at least lateral dimensions of comb structures and outlines of large device structures. First trenches are etched, the first trenches defining the lateral dimensions of the at least comb structures and outlines of large device structures in a single deep etching process. Recession etching may be used on one or two faces of the device wafer for creating structures at least partially recessed below the respective surfaces of the device wafer. A double mask etching process may be used on one or two faces of the device wafer for creating structures at least partially recessed to mutually varying depths from the respective face of the device wafer.

Abstract translation: 在包括单层均质材料的器件晶片上进行微机械器件层的制造方法。 该方法包括在器件晶片的第一面上构图第一掩模，第一掩模至少构图梳状结构的横向尺寸和大型器件结构的轮廓。 蚀刻第一沟槽，第一沟槽在单个深刻蚀工艺中限定至少梳状结构的横向尺寸和大型器件结构的轮廓。 衰减蚀刻可以用在器件晶片的一个或两个面上，用于产生至少部分地凹入器件晶片的相应表面下方的结构。 可以在器件晶片的一个或两个面上使用双掩模蚀刻工艺，用于产生至少部分地凹陷到从器件晶片的相应面相互变化的深度的结构。

公开(公告)号：US20200283292A1

公开(公告)日：2020-09-10

申请号：US16807783

申请日：2020-03-03

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Altti TORKKELI ,  Antti IIHOLA

IPC: B81C1/00 ,  G02B26/08

Abstract: A microelectromechanical structure including a first wafer structure attached by bonding to a second wafer structure. The first wafer structure includes a build part of silicon wafer material, a through via, and an isolation structure separating the through via from the build part. The through via extends between a first electrical contact and a second electrical contact through the first wafer structure in a first direction. The first electrical contact of the first wafer structure is accessible externally and the second electrical contact of the first wafer structure connects to an internal electrical contact on the second wafer structure. In the first direction, the extent of the isolation structure includes a hollow section and a via fill section where the isolation structure is filled with solid electrically insulating material. enables considerable increase of gap height in MEMS structures.

公开(公告)号：US20150336793A1

公开(公告)日：2015-11-26

申请号：US14712987

申请日：2015-05-15

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Altti TORKKELI ,  Antti IIHOLA

IPC: B81C1/00

CPC classification number: B81C1/00412 ,  B81C1/00373 ,  B81C1/00396 ,  B81C1/00404 ,  B81C1/00531 ,  B81C1/00611

Abstract: A method for creating MEMS structures comprises depositing and patterning a first mask on a wafer in order to define desired first areas to be etched in a first trench etching and desired second areas to be etched in a second trench etching. A first intermediate mask is deposited and patterned on top of the first mask. Recession trenches are etched on parts of the wafer. After the first intermediate mask is removed, first trenches are etched with further etching the recession trenches. The first trenches and the recession trenches are filled with a deposit layer. Part of the deposit layer is removed on second areas. A remainder is left on certain areas, to function as a second mask. A third mask is deposited. The third mask defines the final structure. The parts of the wafer on the second areas are etched in the second trench etching. The masks are then removed.

Abstract translation: 一种用于创建MEMS结构的方法包括在晶片上沉积和图案化第一掩模，以便在第一沟槽蚀刻中定义要蚀刻的期望的第一区域和在第二沟槽蚀刻中要蚀刻的期望的第二区域。 在第一掩模的顶部上沉积并图案化第一中间掩模。 在晶片的部分上刻蚀了衰退沟槽。 在去除第一中间掩模之后，第一沟槽被蚀刻，进一步蚀刻凹陷沟槽。 第一个沟渠和经济衰退的沟槽上都铺满了一层沉积层。 部分沉积层在第二个区域被去除。 剩余部分留在某些区域，用作第二个掩模。 存放第三个掩模。 第三个掩码定义了最终结构。 在第二沟槽蚀刻中蚀刻第二区域上的晶片的部分。 然后取下面具。

公开(公告)号：US20240343558A1

公开(公告)日：2024-10-17

申请号：US18632684

申请日：2024-04-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Petteri KILPINEN ,  Marko PEUSSA ,  Antti IIHOLA ,  Altti TORKKELI

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0072 ,  B81B3/001 ,  B81C1/00666 ,  B81C1/00968 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81B2203/0307 ,  B81B2203/04 ,  B81B2207/096 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2203/0109 ,  B81C2203/036

Abstract: A device is provided that includes a handle layer with at least one cavity and suspension structure, a patterned polycrystalline silicon (poly-Si) first device layer, where at least one structural element is suspended by the structure, and may include a seismic element. A second electrically insulating layer is present, followed by a second device layer of patterned single-crystal silicon (mono-Si) with at least one moveably suspended seismic element above the first layer. A cap layer finalizes the structure, with the handle layer, device layers, and the cap layer forming an enclosure's walls. The first and second insulating layers bond the handle and device layers. The enclosure includes at least one seismic element from the second device layer, and at least one static and moveable electrode for motion detection or causation, with the static electrode in the first device layer.