公开(公告)号：US20250132290A1

公开(公告)日：2025-04-24

申请号：US18383108

申请日：2023-10-24

Applicant: SMART Modular Technologies, Inc.

Inventor： Satyanarayan Iyer ,  Torry Steed

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H10B80/00

Abstract: Memory packages are employed in computer processing systems to house memory chips that store data for a processing circuit. The memory chips consume power each time they are accessed, which may be thousands of times per second, which generates heat that needs to be dissipated to avoid high temperatures that may damage memory circuits in the memory chips. The memory packages may include at least one memory chip disposed on a substrate. The memory packages may also include an active cooling device disposed between the memory chips and a package surface to actively conduct heat from the memory chips to the package surface, where it may be dissipated. The active cooling device May be on an opposite side of the memory chips from the substrate or may be disposed in a cavity in the substrate.

公开(公告)号：US20240134757A1

公开(公告)日：2024-04-25

申请号：US18400185

申请日：2023-12-29

Applicant: SMART Modular Technologies, Inc.

Inventor： Torry Steed ,  Kelvin Marino ,  Jinying Shen ,  Itsik Yomorta

IPC: G06F11/14 ,  G06F1/26 ,  G06F1/30

CPC classification number: G06F11/1469 ,  G06F1/263 ,  G06F1/30 ,  G06F11/1451

Abstract: Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system includes: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device through the serial host interface based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device through the serial host interface. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.

公开(公告)号：US10534619B2

公开(公告)日：2020-01-14

申请号：US15055448

申请日：2016-02-26

Applicant: SMART Modular Technologies, Inc.

Inventor： Robert T. Frey

IPC: G06F9/4401

Abstract: A memory management system, and method of operation thereof, includes: a primary device of a resilient storage module configured as a boot device for booting a computer system; an operational status received from the computer system; a secondary device of the resilient storage module configured as the boot device based on the operational status indicating a non-operational state; and a memory module controller of the resilient storage module for initiating a reboot operation using the secondary device as the boot device.

公开(公告)号：US10529688B1

公开(公告)日：2020-01-07

申请号：US15462885

申请日：2017-03-19

Applicant: SMART Modular Technologies, Inc.

Inventor： Satyanarayan Shivkumar Iyer ,  Reuben J. Chang ,  Victor Mahran

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A system and method of manufacture of an integrated circuit device system includes mounting a first elevated device on a first riser positioned adjacent to a base device. The first elevated device includes a first device overhang that extends over the base device. A second elevated device can be mounted on a second riser adjacent to the first riser to allow the attachment of a second elevated device mounted above the first elevated device to achieve higher component densities.

公开(公告)号：US10474362B2

公开(公告)日：2019-11-12

申请号：US15294678

申请日：2016-10-14

Applicant: SMART Modular Technologies, Inc.

Inventor： Victor Y. Tsai ,  Robert Fillion

IPC: G06F3/06 ,  G06F12/02

Abstract: Approaches, techniques, and mechanisms are disclosed for a method of operation of a Flash-based block storage system including: transferring a first data to a logical block address; storing the first data in a physical block, of a storage array, associated with the logical block address; receiving a trim command for the logical block address; establishing a reserved physical block associated with the logical block address of the trim command; transferring second data for writing to the logical block address of the trim command; releasing the reserved physical block associated with the logical block address; and writing the second data to the logical block address.

公开(公告)号：US10409754B2

公开(公告)日：2019-09-10

申请号：US15141757

申请日：2016-04-28

Applicant: SMART Modular Technologies, Inc.

Inventor： Rajesh Ananthanarayanan

IPC: G06F13/38 ,  G06F13/40 ,  G06F3/06

Abstract: An interconnected memory system, and a method of operation thereof, including: a first discrete unit having a first unit processor and first unit memory module; a high-speed interconnect connected directly to the first unit memory module; and a second discrete unit having a second unit processor and a second unit memory module, the second unit memory module connected to the first unit memory module through the high-speed interconnect for utilizing the first unit memory module and the second unit memory module with the first unit processor.

公开(公告)号：US09939855B2

公开(公告)日：2018-04-10

申请号：US14942787

申请日：2015-11-16

Applicant: SMART Modular Technologies, Inc.

Inventor： Victor Mahran ,  Robert S. Pauley, Jr.

IPC: G06F1/18 ,  H05K7/14 ,  H05K1/14 ,  G06F1/20 ,  G11C5/02 ,  H05K1/02

CPC classification number: G06F1/185 ,  G06F1/20 ,  G11C5/025 ,  H05K1/0209 ,  H05K1/144 ,  H05K1/145 ,  H05K7/1431 ,  H05K2201/042 ,  H05K2201/10159 ,  H05K2201/10303 ,  H05K2201/10378 ,  H05K2201/10409 ,  Y10T29/4913

Abstract: A method of manufacture of an enhanced capacity memory system includes: providing a dual in-line memory module carrier having a memory module and an integrated memory buffer coupled to the memory module; coupling a memory expansion board, having a supplementary memory module, to the dual in-line memory module carrier including attaching a bridge transposer; and providing a system interface connector coupled to the integrated memory buffer and the bridge transposer for controlling the memory module, the supplementary memory module, or a combination thereof.

公开(公告)号：US09754634B2

公开(公告)日：2017-09-05

申请号：US13303863

申请日：2011-11-23

Applicant: Jinying Shen ,  Robert Tower Frey ,  Kelvin Marino ,  Joshua Harris Brooks

Inventor： Jinying Shen ,  Robert Tower Frey ,  Kelvin Marino ,  Joshua Harris Brooks

IPC: G11C5/14

CPC classification number: G11C5/141 ,  Y10T29/49117

Abstract: A method of manufacture of the memory management system includes: fabricating a dual in-line memory module carrier; mounting a volatile memory device on the dual in-line memory module carrier; mounting a non-volatile memory on the dual in-line memory module carrier on a side opposite the volatile memory device; mounting an uninterruptible power supply on the dual in-line memory module carrier for maintaining a memory module power when a system power input decays; and mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply for copying data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects the decay of the system power input to a first cross-over level.

公开(公告)号：US09424188B2

公开(公告)日：2016-08-23

申请号：US13303818

申请日：2011-11-23

Applicant: Mike H. Amidi ,  Michael Rubino ,  Alessandro Fin

Inventor： Mike H. Amidi ,  Michael Rubino ,  Alessandro Fin

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/16 ,  G06F3/06

CPC classification number: G06F12/0804 ,  G06F3/0661 ,  G06F13/16 ,  G06F2212/2022 ,  G06F2212/3042

Abstract: A method of operation of a non-volatile memory packaging system includes: addressing an integrated circuit package having a system interface; accessing a module controller, in the integrated circuit package, through system interface; accessing a random access memory, in the integrated circuit package, by the module controller for storing data from the system interface; writing to a non-volatile memory, in the integrated circuit package by the module controller, with the data from the random access memory; and monitoring an address look-up register, by the module controller, for reading the data from the non-volatile memory or the random access memory through the system interface.

Abstract translation: 非易失性存储器封装系统的操作方法包括：寻址具有系统接口的集成电路封装; 通过系统接口访问集成电路封装中的模块控制器; 通过模块控制器访问集成电路封装中的随机存取存储器，用于存储来自系统接口的数据; 在模块控制器的集成电路封装中写入来自随机存取存储器的数据的非易失性存储器; 以及由模块控制器监视地址查找寄存器，用于通过系统接口从非易失性存储器或随机存取存储器读取数据。

公开(公告)号：US20130083473A1

公开(公告)日：2013-04-04

申请号：US13633074

申请日：2012-10-01

Applicant: SMART MODULAR TECHNOLOGIES, INC.

Inventor： Victor Mahran ,  Robert S. Pauley, JR.

IPC: H05K7/10 ,  H05K3/30

CPC classification number: G06F1/185 ,  G06F1/20 ,  G11C5/025 ,  H05K1/0209 ,  H05K1/144 ,  H05K1/145 ,  H05K7/1431 ,  H05K2201/042 ,  H05K2201/10159 ,  H05K2201/10303 ,  H05K2201/10378 ,  H05K2201/10409 ,  Y10T29/4913

Abstract: A method of manufacture of an enhanced capacity memory system includes: providing a dual in-line memory module carrier having a memory module and an integrated memory buffer coupled to the memory module; coupling a memory expansion board, having a supplementary memory module, to the dual in-line memory module carrier including attaching a bridge transposer; and providing a system interface connector coupled to the integrated memory buffer and the bridge transposer for controlling the memory module, the supplementary memory module, or a combination thereof

Abstract translation: 一种制造增强容量存储器系统的方法包括：提供具有存储器模块和耦合到存储器模块的集成存储器缓冲器的双列直插存储器模块载体; 将具有辅助存储器模块的存储器扩展板耦合到双列直插式存储器模块载体，包括附接桥式变压器; 并且提供耦合到集成存储器缓冲器的系统接口连接器和用于控制存储器模块，辅助存储器模块或其组合的桥接转换器