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    Sense amplifier
    1.
    发明授权
    Sense amplifier 失效
    感应放大器

    公开(公告)号：US3879621A

    公开(公告)日：1975-04-22

    申请号：US35214373

    申请日：1973-04-18

    Applicant: IBM

    Inventor： CAVALIERE JOSEPH RICHARD ,  SCARPERO JR WILLIAM JOHN

    IPC: G11C11/41 ,  G11C11/409 ,  G11C11/419 ,  H03F3/18 ,  H03K5/02 ,  H03K19/017 ,  H03K3/281

    CPC classification number: G11C11/419 ,  H03K5/023

    Abstract: An FET sense amplifier for converting a double rail differential memory output signal to a full logic output signal, the amplifier comprising first and second pairs of FETs coupled together at a pair of common nodes. In one embodiment, first and second field effect transistors of the same conductive type are connected to respective ones of the nodes. A third field effect transistor of a second conductive type is connected to one of the pairs of FETs, the first, second and third field effect transistors are interconnected so that when the first and second transistors conduct the third transistor is cut off, and when the first and second transistors are cut off, the third transistor conducts.

    Abstract translation: 一种用于将双轨差分存储器输出信号转换为全逻辑输出信号的FET读出放大器，该放大器包括在一对公共节点处耦合在一起的第一和第二对FET。 在一个实施例中，相同导电类型的第一和第二场效应晶体管连接到相应的节点。 第二导电类型的第三场效应晶体管连接到FET对中的一个，第一，第二和第三场效应晶体管互连，使得当第一和第二晶体管导通第三晶体管被切断时，并且当 第一和第二晶体管被切断，第三晶体管导通。

    5.
    发明专利
    未知

    公开(公告)号：DE68923334D1

    公开(公告)日：1995-08-10

    申请号：DE68923334

    申请日：1989-09-12

    Applicant: IBM

    Inventor： CAVALIERE JOSEPH RICHARD ,  SMITH GEORGE EARL

    IPC: H03K19/00 ,  H03K19/003 ,  H03K19/086

    Abstract: A current switch emitter-follower logic circuit allows both the UP output logic level and the DOWN output logic level to be independently controlled with respect to a fixed reference voltage so as to permit very small output level swings. A feedback circuit (40) generates two different control signals (VCS, VCCC) which are independently variable and are input to a control circuit (42) and to a logic circuit (1) to compensate for fluctuations in power supply voltages, temperature and circuit parameters. These control signals are applied to a variable current source within the logic circuit and to a dynamic resistance within the control circuit to compensate almost instantaneously to fluctuations in power supply voltage, temperature or circuit device parameters, maintaining the logic circuit output levels close to reference levels so as to permit small output signal swings. The output logic levels need not be symmetrical around a central reference point.

    EMITTER FOLLOWER LOGIC CIRCUIT
    6.
    发明专利
    EMITTER FOLLOWER LOGIC CIRCUIT 未知

    公开(公告)号：DE3066688D1

    公开(公告)日：1984-03-29

    申请号：DE3066688

    申请日：1980-07-10

    Applicant: IBM

    Inventor： CAVALIERE JOSEPH RICHARD ,  HENLE ROBERT ATHANASIUS ,  KONIAN RICHARD ROBERT ,  WALSH JAMES LEO

    IPC: H03K19/082 ,  H03K19/086 ,  H03K19/013

    Abstract: A high speed, unity gain, emitter follower OR circuit is disclosed including first and second pairs of emitter-connected complementary bipolar transistors with the bases of the NPN transistors being connected together and the bases of the PNP transistors being connected commonly to an input line. One of the NPN transistors id diode-connected (base to collector). The emitter of the other NPN transistor is connected to an output terminal. The input line is connected to the emitters of a pair of OR input NPN transistors and to a first current source. A second current source is coupled to the diode-connected NPN transistor.

    7.
    发明专利
    未知

    公开(公告)号：DE3685546T2

    公开(公告)日：1993-01-28

    申请号：DE3685546

    申请日：1986-10-17

    Applicant: IBM

    Inventor： CAVALIERE JOSEPH RICHARD ,  CHANG ALBERT YUAN

    IPC: H04L5/14

    Abstract: A simultaneous bi-directional transceiver is described. The transceiver comprises two circuits (1; 2) which are disposed at opposite ends of an interchip cable (1000). In response to the application of digital data signals to these circuits, they generate a trilevel voltage at the ends of the interchip cable. Then, in each circuit, a first input to a differential amplifier is generated from the trilevel voltage by a level shifter comprising a first diode (T8; T28) and a first constant current sink (T6, R7; T26, R27) and a second input to the differential amplifier is derived from the digital data input signal applied to that circuit by a level shifter comprising a second diode (T7; T27) and a second constant current source (T5, R5; T25, R25). Finally, the transceiver outputs (lines 107, 207) are generated from the differential amplifier outputs.

    10.
    发明专利
    未知

    公开(公告)号：DE3774372D1

    公开(公告)日：1991-12-12

    申请号：DE3774372

    申请日：1987-07-28

    Applicant: IBM

    Inventor： ASHTON GERARD JOHN ,  CAVALIERE JOSEPH RICHARD ,  CHENG MING TOCK

    IPC: H03K19/013 ,  H03K19/086 ,  H03K19/0952

    Abstract: A logic circuit network with circuitry for independently controlling at least one of the logic levels generated thereby, comprising, in one embodiment, a logic circuit with an output current node, a complement output current node, and at least one input line, the circuit for generating an output voltage level at the output current node which depends on the amount of current drawn therethrough, and for generating a complement output voltage level at the complement output current node which depends on the amount of current drawn therethrough; in combination with a current drawing means for drawing a controlled amount of current through one of those nodes to adjust the voltage level at that node. In one embodiment, this current drawing means is connected to a voltage reference level VR1, and operates to draw an amount of current from whichever current node is at a voltage level which is closest to a predetermined constant plus this voltage reference level VR1. The amount of current drawn is controlled to cause this closest node voltage level to approach this predetermined constant plus VR1. In a preferred embodiment this current drawing means comprises a separate differential amplifier connected to each of the output current nodes.

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