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    ARRANGEMENT IN THE INSTRUCTION UNIT OF A MICROPROGRAM- CONTROLLED PROCESSOR FOR THE DIRECT HARDWARE- CONTROLLED EXECUTION OF PARTICULARINSTRUCTIONS
    1.
    发明专利
    ARRANGEMENT IN THE INSTRUCTION UNIT OF A MICROPROGRAM- CONTROLLED PROCESSOR FOR THE DIRECT HARDWARE- CONTROLLED EXECUTION OF PARTICULARINSTRUCTIONS 未知

    公开(公告)号：CA1191615A

    公开(公告)日：1985-08-06

    申请号：CA429597

    申请日：1983-06-03

    Applicant: IBM

    Inventor： CHILINSKI HERBERT ,  GETZLAFF KLAUS J ,  HAJDU JOHANN ,  RAETH FRANZ J

    IPC: G06F9/22 ,  G06F9/26 ,  G06F9/30 ,  G06F9/318

    Abstract: ARRANGEMENT IN THE INSTRUCTION UNIT OF A MICROPROGRAM-CONTROLLED PROCESSOR FOR THE DIRECT HARDWARE-CONTROLLED EXECUTION OF PARTICULAR INSTRUCTIONS In a microprogram-controlled processor, having an additional operating mode in which particular functions can be executed under direct hardware control, a mode latch is provided signalizing the instruction decoder whether micro program instructions or directly controlled macro instructions are to be executed. The microprogram instructions are executed in the usual manner. For the execution of the directly controlled macro instructions, the control storage of the processor is not required for supplying micro instructions. Instead, this storage with the operation decoder as an address supplies one or several hardware control words. The hardware control words consist of individual control bits, each of which directly controls one hardware function.

    2.
    发明专利
    未知

    公开(公告)号：BR8404462A

    公开(公告)日：1985-09-03

    申请号：BR8404462

    申请日：1984-09-05

    Applicant: IBM

    Inventor： CHILINSKI HERBERT ,  GETZLAFF KLAUS J ,  HAJDU JOHANN ,  RICHTER STEPHAN

    IPC: G06F9/38 ,  G06F11/14 ,  G06F9/46

    Abstract: In the processing of instructions in data processing systems it is not always possible to execute these instructions without interruption since particular situations, in the following called events can occur which necessitate a short interruption for executing the operations caused by such events before continuing the interrupted instruction processing. Such repetition however is only possible when the contents of the operation register containing the instruction is frozen during the interruption. Such a situation requires two actions: the first is the execution of a forced operation to resolve the event. The second action is a repetition of the instruction and execution phase of the interrupted instruction.

    ARRANGEMENT FOR MICRO INSTRUCTION CONTROL
    3.
    发明专利
    ARRANGEMENT FOR MICRO INSTRUCTION CONTROL 未知

    公开(公告)号：CA1103366A

    公开(公告)日：1981-06-16

    申请号：CA312702

    申请日：1978-10-04

    Applicant: IBM

    Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT

    IPC: G06F9/22 ,  G06F9/00

    Abstract: ARRANGEMENT FOR MICRO INSTRUCTION CONTROL In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

    4.
    发明专利
    未知

    公开(公告)号：FR2406851A1

    公开(公告)日：1979-05-18

    申请号：FR7828926

    申请日：1978-10-02

    Applicant: IBM

    Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH R ,  HAJDU JOHANN ,  IRRO FRITZ ,  NEUBER SIEGFRIED ,  WILLE UDO

    IPC: G06F9/22 ,  G06F9/16

    Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

    9.
    发明专利
    未知

    公开(公告)号：FR2406851B1

    公开(公告)日：1986-04-11

    申请号：FR7828926

    申请日：1978-10-02

    Applicant: IBM

    Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH R ,  HAJDU JOHANN ,  IRRO FRITZ ,  NEUBER SIEGFRIED ,  WILLE UDO

    IPC: G06F9/22

    Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

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