公开(公告)号：EP1671358A4

公开(公告)日：2009-10-21

申请号：EP04789450

申请日：2004-09-30

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  RAMACHANDRAN VIDHYA

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1792343A4

公开(公告)日：2009-11-11

申请号：EP05754954

申请日：2005-05-26

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  FEILCHENFELD NATALIE ,  GAUTSCH MICHAEL L ,  HE ZHONG-XIANG ,  MOON MATTHEW D ,  RAMACHANDRAN VIDHYA ,  WATERHOUSE BARBARA

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/20 ,  H01L23/522 ,  H01L27/01 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10T29/49002 ,  H01L2924/00

公开(公告)号：EP1974379A4

公开(公告)日：2011-06-01

申请号：EP07710226

申请日：2007-01-19

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  DOWNES KEITH E ,  LINDGREN PETER J ,  STAMPER ANTHONY K

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76832 ,  H01L23/5223 ,  H01L28/60 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1839340A4

公开(公告)日：2009-09-09

申请号：EP05855611

申请日：2005-12-22

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  FURKAY STEPHEN S ,  JOHNSON JEFFREY B ,  RASSEL ROBERT M

IPC: H01L21/20 ,  H01L29/93

CPC classification number: H01L29/93

Abstract: A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction.

公开(公告)号：JP2002368147A

公开(公告)日：2002-12-20

申请号：JP2002101203

申请日：2002-04-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： COOLBAUGH DOUGLAS D ,  LANZEROTTI LOUIS D ,  MALINOWSKI JOHN C

IPC: H01L29/73 ,  G03F9/00 ,  H01L21/265 ,  H01L21/266 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L23/544 ,  H01L27/06

CPC classification number: G03F9/708 ,  G03F9/7084 ,  H01L21/8249 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a BiCMOS device comprising a deep sub-collector region and a self-aligning mark. SOLUTION: There are provided a step (a) where a layer with a first pattern comprising a thick dielectric material is formed on the surface of a material stack formed on a semiconductor substrate through lithography, a step (b) where high energy/high dose injection is performed via an opening of the first layer as well as the material stack to form at least one deep sub-collector region in the semiconductor substrate, a step (c) where a layer with a second pattern (photoresist or dielectrics) is formed by lithography, and a step (d) where etching is performed through the material stack for forming an alignment mark in the semiconductor substrate, which is positioned below, using the layer with the first pattern as an alignment mark mask.

Abstract translation: 要解决的问题：提供一种用于形成包括深子集电极区域和自对准标记的BiCMOS器件的方法。 解决方案：提供了一种步骤（a），其中通过光刻在形成在半导体衬底上的材料堆叠的表面上形成具有包括厚电介质材料的第一图案的层，步骤（b），其中高能量​​/高剂量 通过第一层的开口以及材料堆叠进行注入以在半导体衬底中形成至少一个深的亚极集电极区域;步骤（c），其中形成具有第二图案的层（光致抗蚀剂或电介质） 以及步骤（d），其中使用具有第一图案的层作为对准标记掩模，通过材料堆叠进行蚀刻以在位于下方的半导体衬底中形成对准标记。

公开(公告)号：JP2006196894A

公开(公告)日：2006-07-27

申请号：JP2006001619

申请日：2006-01-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HOOK TERENCE B ,  RASSEL ROBERT M ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K ,  MURPHY WILLIAM J

IPC: H01L23/36 ,  H01L23/373

CPC classification number: H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a resistor that has a heat sink with excellent heat conduction. SOLUTION: This heat sink includes a conduction path that has a high-thermal conductivity metal and other thermal conductors. In order that an electrical resistor may not be short-circuited to earth by this thermal resistor, a thin layer with a high-thermal conductivity electric insulator is interposed between the thermal conductor and the resistor's body. Accordingly, since heat is conducted to the heat sink in a direction in which the thermal conductor with high thermal conductivity moves away from the resistor, the resistor can pass a large amount of current. In addition to the fact that a parasitic capacitance and other electric parasitic actions that help reduce high-frequency responses from the electric resistor are lowered, various structures of a thermal conductor and heat sink are achieved through which favorable thermal conduction characteristics are obtained. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有散热器的具有优异热传导性的电阻器。 解决方案：该散热器包括具有高导热性金属和其他热导体的导电路径。 为了使该电阻器不会被该热电阻器短路到地，具有高导热电绝缘体的薄层插入在热导体和电阻体之间。 因此，由于在热导率高的导体从电阻器移开的方向向散热器传导热量，所以电阻器能够通过大量的电流。 除了有助于降低来自电阻器的高频响应的寄生电容和其他电寄生作用降低之外，还实现了热导体和散热器的各种结构，从而获得了良好的热传导特性。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：EP1671362A4

公开(公告)日：2010-04-28

申请号：EP04789451

申请日：2004-09-30

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  GREER HEIDI L ,  RASSEL ROBERT M

IPC: H01L21/02 ,  H01L20060101 ,  H01L21/302 ,  H01L21/461 ,  H01L27/07 ,  H01L27/08

CPC classification number: H01L27/0738 ,  H01L27/0802 ,  H01L28/20

公开(公告)号：EP1794778A4

公开(公告)日：2009-06-03

申请号：EP05779566

申请日：2005-08-04

Applicant: IBM

Inventor： CHINTHAKINDI ANIL K ,  COOLBAUGH DOUGLAS D ,  RAMACHANDRAN VIDHYA ,  RASSEL ROBERT M

IPC: H01L21/20

CPC classification number: H01L28/24 ,  H01L27/0629 ,  H01L29/7833

Abstract: A FEOL/MEOL metal resistor (32) that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors as well as various methods of integrating such a metal resistor structure (32) into a CMOS technology are provided.

公开(公告)号：EP1800343A4

公开(公告)日：2008-11-19

申请号：EP05782737

申请日：2005-08-05

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  HERSHBERGER DOUGLAS B ,  RASSEL ROBERT M

IPC: H01L29/93 ,  H01L29/94

CPC classification number: H01L29/93 ,  H01L29/94

Abstract: The present invention provides a varactor (22) that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor (22). The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate (12) of a first conductivity type and optionally a subcollector (14) or isolation well (i.e., doped region) of a second conductivity type located below an upper region (11) of the substrate (12), the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions (16) are formed in the upper region (11) of the substrate (12) and then a well region is formed in the upper region (11) of the substrate (12). In some cases, the doped region (14) is formed at this point of the inventive process. The well region includes outer well regions (20A and 20C) of the second conductivity type and an inner well region (20B) of the first conductivity type. Each well of said well region is separated at an upper surface by an isolation region (16). A field effect transistor having at least a gate conductor (26) of the first conductivity type is then formed above the inner well region (20B).

公开(公告)号：WO2007084982A8

公开(公告)日：2008-07-10

申请号：PCT/US2007060767

申请日：2007-01-19

Applicant: IBM ,  COOLBAUGH DOUGLAS D ,  DOWNES KEITH E ,  LINDGREN PETER J ,  STAMPER ANTHONY K

Inventor： COOLBAUGH DOUGLAS D ,  DOWNES KEITH E ,  LINDGREN PETER J ,  STAMPER ANTHONY K

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76832 ,  H01L23/5223 ,  H01L28/60 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and semiconductor device. In the method, at least one partial via (26) is etched in a stacked structure and a border (32) is formed about the at least one partial via (26). The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer (22).

Abstract translation: 一种方法和半导体器件。 在该方法中，至少一个部分通孔（26）以堆叠结构被蚀刻，并且围绕至少一个部分通孔（26）形成边界（32）。 该方法还包括使用选择性蚀刻执行厚布线，同时继续蚀刻至少一个蚀刻停止层（22）。