公开(公告)号：JP2007306008A

公开(公告)日：2007-11-22

申请号：JP2007141486

申请日：2007-05-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CYRILLE CABRAL JR ,  CLEVENGER LAWRENCE ,  HSU LOUIS ,  WONG KEITH KWONG HON

IPC: H01L21/8242 ,  C23C14/00 ,  C23C14/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/318 ,  H01L27/108

CPC classification number: H01L28/75 ,  C23C14/0073 ,  C23C14/0641 ,  H01L21/2855 ,  H01L21/28568

Abstract: PROBLEM TO BE SOLVED: To provide the method of forming a capacitor on an original position in a semiconductor structure.
SOLUTION: First, a previously-treated semiconductor substrate is positioned in a sputtering chamber. Then, Ar gas is flown into the sputtering chamber and a first heat-resistant metal-silicon-nitrogen layer is adhered in a sputtering manner onto the substrate from the target of heat-resistant metal silicide or two targets of heat-resistant metal and silicon. Then, N
2 gas is flown into the sputtering chamber until the density of N
2 gas in the chamber reaches at least 35%, and a second heat-resistant metal-silicon-nitrogen layer is adhered in the sputtering manner onto the first heat-resistant metal-silicon-nitrogen layer. Then, the flow of N
2 gas is stopped and a third heat-resistant metal-silicon-nitrogen layer is adhered in the sputtering manner onto the second heat-resistant metal-silicon-nitrogen layer. Then, the multilayer stack of heat-resistant metal-silicon-nitrogen is formed on the capacitor using photolithography.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供在半导体结构中的原始位置形成电容器的方法。 解决方案：首先，将预先处理的半导体衬底放置在溅射室中。 然后，将Ar气体流入溅射室，并且将第一耐热金属硅 - 氮层从耐热金属硅化物的靶或两个耐热金属和硅的靶以溅射方式附着到基板上 。 然后，将N 2 气体流入溅射室，直到室内的N 2 SB 2气体的密度达到至少35％，而第二耐热金属硅 - 氮层以溅射方式粘附到第一耐热金属 - 硅 - 氮层上。 然后，停止N SB 2气体的流动，并且以溅射方式将第三耐热金属 - 硅 - 氮层粘附到第二耐热金属 - 硅 - 氮层上。 然后，使用光刻法在电容器上形成多层叠层的耐热金属硅 - 氮。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JPH10242082A

公开(公告)日：1998-09-11

申请号：JP1837998

申请日：1998-01-30

Applicant: IBM

Inventor： PANAYOTIS CONSTANTINO ANDRICAK ,  CYRILLE CABRAL JR ,  ROY CAROTHERS ,  ALFRED GRILL ,  CATHRIN SENJER

IPC: H01L21/288 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To remove a conductive noble metal plating base from a noble metal patterned electrodeposit region dissimilar to this base, by selecting a multilayered metal material to be alloyed or mixed in the annealing condition. SOLUTION: A structure includes a base 2 having a blanket mat layer of a plating base 1 having electrodeposit features including a noble metal 4 dissimilar to the base plating layer material. The noble metal deposit is electroplated using a mask to be removed later. Selective etching removes the base 1 not alloyed in a region between the features to form a structure. An anneal process is long enough to obtain a good alloy 6 but short enough to prevent the base from becoming excessively dense at the edge of the electrodeposit and the electrodeposit from excessively diffusing laterally in the base region between the features.

公开(公告)号：JP2005167251A

公开(公告)日：2005-06-23

申请号：JP2004349278

申请日：2004-12-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CYRILLE CABRAL JR ,  KEDZIERSKI JAKUB T ,  KU VICTOR ,  LAVOIE CHRISTIAN ,  NARAYANAN VIJAY ,  STEEGEN AN L

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/823835

Abstract: PROBLEM TO BE SOLVED: To minimize the associated complexity and cost in fabricating a CMOS structure containing silicide contacts and metal silicide gates.
SOLUTION: The method of integrating the silicide metal of a CMOS allows incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-alignment process (salicide) and at least one lithography process. The integration method allows at least two different thicknesses of metals deposited on a semiconductor substrate such that on some of the CMOS transistors thinner silicide metals are formed and used in the formation of gate contacts, whereas on the other CMOS transistors thicker silicide metals are formed and used in the formation of metal silicide gates. The integration method of the present invention can also be used to form multiple phases of metal silicide gates by varying the metal deposition thickness thus having differing amounts of metal present during metal gate formation.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了最小化制造包含硅化物接触和金属硅化物栅极的CMOS结构的相关复杂性和成本。 解决方案：集成CMOS的硅化物金属的方法允许使用自对准工艺（自对准硅化物）和至少一个光刻工艺并入硅化物触点（S / D和栅极）和金属硅化物栅极。 积分方法允许沉积在半导体衬底上的至少两种不同厚度的金属，使得在一些CMOS晶体管上形成较薄的硅化物金属，并用于形成栅极触点，而在另一个CMOS晶体管上形成更厚的硅化物金属， 用于形成金属硅化物门。 本发明的积分方法还可用于通过改变金属沉积厚度从而在金属栅极形成期间存在不同量的金属来形成金属硅化物栅极的多相。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2003060084A

公开(公告)日：2003-02-28

申请号：JP2002149960

申请日：2002-05-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CYRILLE CABRAL JR ,  CLEVENGER LAWRENCE ,  HSU LOUIS ,  WONG KEITH KWONG HON

IPC: C23C14/00 ,  C23C14/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/75 ,  C23C14/0073 ,  C23C14/0641 ,  H01L21/2855 ,  H01L21/28568

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a capacitor at a source position inside a semiconductor structure.
SOLUTION: In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to deposit by sputtering a first refractory metal-silicon-nitrogen layer 14 on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N
2 gas is then flown into the sputtering chamber until that the concentration of N
2 gas in the camber is at least 35% to deposit by sputtering a second refractory metal-silicon-nitrogen layer 16 on top of the first refractory metal-silicon-nitrogen layer. The N
2 gas flow is then stopped to deposit by sputtering a third refractory metal-silicon-nitrogen layer 18 on top of the second refractory metal-silicon-nitrogen layer. The multi- layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into the capacitor.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种在半导体结构内的源极位置形成电容器的方法。 解决方案：在该方法中，首先将预处理的半导体衬底放置在溅射室中。 然后通过从难熔金属硅化物靶或从难熔金属和硅的两个靶溅射基底上的第一难熔金属硅 - 氮层14，将Ar气体流入溅射室中。 然后将N 2气体流入溅射室，直到通过在第一耐火金属 - 硅 - 氮层的顶部溅射第二难熔金属 - 硅 - 氮层16来沉积外弧中的N 2气体的浓度至少为35％ 。 然后通过在第二难熔金属 - 硅 - 氮层的顶部溅射第三耐火金属 - 硅 - 氮层18来停止N2气流以沉积。 然后将难熔金属硅 - 氮的多层堆叠光刻形成电容器。

公开(公告)号：JP2002353246A

公开(公告)日：2002-12-06

申请号：JP2002110367

申请日：2002-04-12

Applicant: IBM

Inventor： CYRILLE CABRAL JR ,  KEVIN K CHAN ,  COHEN GUY MOSHE ,  GUARINI KATHRYN WILDER ,  LAVOIE CHRISTIAN ,  PAUL MICHAEL SOLOMON ,  ZHANG YING

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a self-aligned silicide process applicable to contacting silicon, sidewall, source, and drain. SOLUTION: A method (and a structure formed by using this method) to form a metal silicide contact on a non-planar silicon-containing area which limits the silicon consumption at a silicon-containing area includes: forming a blanket metal layer over the silicon-containing area, forming a silicon layer over the metal layer, performing an selective and anisotropical etching of the silicon layer against the metal, forming a metal silicon alloy by reacting the metal and silicon at a first temperature, etching away any unreacted metal layer, forming a metal-Si2 alloy by annealing at a second temperature, and selectively etching away any unreacted silicon layer.

公开(公告)号：JP2001274112A

公开(公告)日：2001-10-05

申请号：JP2001055239

申请日：2001-02-28

Applicant: IBM

Inventor： CYRILLE CABRAL JR ,  ROY ARTHUR KARAZAASU ,  HARPER JAMES MCKELL EDWIN ,  PAUL MICHAEL KOZLOSKY ,  CHRISTIAN LEIBOW ,  JOSEPH SCOTT NEWBERG ,  RONEN ANDREW ROVU

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a metal silicide contact holding a resistance value within the present operating standard, while the high temperature stability is increased. SOLUTION: Prior to activating a source-drain region in the structure, at least an alloying element is added to a metal capable of forming a metal silicide, by annealing and alloyed to obtain a metal alloy silicide contact without agglomeration. A complementary metal oxide semiconductor(CMOS) device, having a metal silicide contact which is durable against high-temperature annealing used for activating the source-drain region of the device is provided by adding at least an alloy element to an initial metal layer used for forming the silicide.