公开(公告)号：WO03005447A8

公开(公告)日：2004-02-19

申请号：PCT/GB0202961

申请日：2002-06-27

Applicant: IBM ,  IBM UK ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMACHANDRA ,  GRUENING ULRIKE ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10894

Abstract: A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.

Abstract translation: 用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域中制造具有硅化多晶硅层的垂直MOSFET DRAM单元，着陆焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠。 该工艺消除了对M0金属化层的需要。

公开(公告)号：WO03005447A2

公开(公告)日：2003-01-16

申请号：PCT/GB0202961

申请日：2002-06-27

Applicant: IBM ,  IBM UK ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMACHANDRA ,  GRUENING ULRIKE ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10894

Abstract: A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.

Abstract translation: 用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域，连接焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠中制造具有硅化多晶硅层的垂直MOSFET DRAM单元。 该工艺消除了对M0金属化层的需求。

公开(公告)号：JP2002026143A

公开(公告)日：2002-01-25

申请号：JP2001127022

申请日：2001-04-25

Applicant: IBM

Inventor： GRUENING ULRIKE ,  JAMMY RAJARAO ,  TEWS HELMUT

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To make the thickness of an oxide layer uniform by reducing crystal direction dependency as to a method for forming an oxide layer on the sidewall of a trench formed in a substrate. SOLUTION: This method has a stage, where the trench 200 is formed in the substrate 24, a stage where a nitride interface layer 1250 covering at least part of the sidewall 32 of the trench 200 is formed, a stage where an amorphous layer covering the nitride interface layer 1250 is formed, and a stage where an oxide layer 160 is formed by oxidizing the amorphous layer. Here, a separate collar 130 is arranged, by covering a separate collar nitride interface barrier layer 125 provided between a separate collar oxide layer and the trench sidewall 32, and a vertical gate oxide film 160 is arranged, covering the gate nitride interface layer 1250 provided between the gate oxide layer and trench sidewall 32.

公开(公告)号：JP2001035860A

公开(公告)日：2001-02-09

申请号：JP2000179287

申请日：2000-06-15

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  KARL J REEDENSU

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To solve the problems associated with strap formation (e.g. conductive connection between a storage device and the gate-drain of a transistor) by connecting a transistor electrically with a storage capacitor through the outward diffusion region of a conductive strap. SOLUTION: A conductive strap 800 extends laterally from a vertical storage capacitor 103. A channel region 1300 is located on the outside of the vertical storage capacitor 103 and extending along a vertical surface shifted laterally therefrom. In the operation, the voltage on one gate conductor of a gate conductor stack causes to conduct a P well adjacent to a step part 1300 in a substrate to form a connection between two diffusion regions (e.g. source and drain). In the process, electrical connection is made between the contact bit line and the storage device 103 through a vertical transistor formed along the strap 1300 through the strap 800.

公开(公告)号：JPH11330402A

公开(公告)日：1999-11-30

申请号：JP9246899

申请日：1999-03-31

Applicant: SIEMENS AG ,  IBM

Inventor： GRUENING ULRIKE ,  JAIPRAKASH VENKATACHALAM C ,  BRONNER GARY ,  RADENS CARL ,  BEINTNER JOCHEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce the diffusion of the height of an embedded strap by making the depression extending below the surface of the substrate in a filling material, to determine the top surface of a buried strap and by making a recess extending below the top surface of the embedded strap in a collar to determine the bottom side surface. SOLUTION: A substrate includes a partially completed trench capacitor. A collar 110 is made on the upper portion of the trench capacitor. A trench 108 is filled with a filling material 112 and the inner sidewall of the collar is lined with the filling material 112. A recess having a predetermined depth is made in the filling material 112. The depth of the recess actually determines the top portion of an embedded strap. A hole is made in the collar to the depth of 120 below the top surface 118 of the filling material 112. A layer 122 is removed from the side of the trench 108 and the top surface of a semiconductor device 100, while a recessed region 124 filled with the material of the layer 122 is left.

公开(公告)号：WO0201607A3

公开(公告)日：2002-05-23

申请号：PCT/US0120206

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  BERGNER WOLFGANG ,  BRONNER GARY B ,  GRUENING ULRIKE ,  KUDELKA STEPHEN ,  MICHAELIS ALEXANDER ,  NESBIT LARRY ,  RADENS CARL J ,  SCHLOESSER TILL ,  TEWS HEOMUT HORST

IPC: H01L21/8242

CPC classification number: H01L27/10864

Abstract: A method for clearing an isolation collar (5) from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A insulating material is deposited above a node conductor (3) of the storage capacitor. A layer of silicon (9) is deposited over the barrier material. Dopant ions are implanted at an angle (11) into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

Abstract translation: 一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环（5）的方法，同时将隔离套环留在深沟槽的其他表面。 绝缘材料沉积在存储电容器的节点导体（3）的上方。 一层硅（9）沉积在阻挡材料上。 将掺杂离子以角度（11）注入到深沟槽内的沉积硅层中，从而留下沉积的硅，沿着深沟槽的一侧不被植入。 未投影的硅被蚀刻。 隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

公开(公告)号：JP2000323684A

公开(公告)日：2000-11-24

申请号：JP2000085406

申请日：2000-03-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  HALLE SCOTT ,  RADENS CARL J ,  JEFFREY J WERSER ,  BEINTNER JOCHEN ,  MANDELMAN JACK A ,  WITTMANN JUERGEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To form a trench capacitor in a semiconductor body. SOLUTION: A trench capacitor 10 and a MOS transistor 9 are provided in a substrate 16 to form a cell 8 of the DRAM, and the cell 8 is separated from adjacent cells by an STI region 28. The capacitor 10 is composed of an insulator 14 enveloping the trench and a first electrode 24 filled with polysilicon 12, is connected to the drain portion 72 through a buried electrode 22, and is insulated from a gate electrode 20 by a dielectric 23. A second electrode 25 is formed in its bottom portion through an insulator 14. A transistor 9 has N-type drain 72 and source 71 in an upper active region 11 of the substrate 16 and operates with a p well as channel.

公开(公告)号：JP2000183302A

公开(公告)日：2000-06-30

申请号：JP35805299

申请日：1999-12-16

Applicant: IBM ,  SIEMENS AG

Inventor： SUSAN E SHARUU ,  TSUE CHIAN CHEN ,  JONATHAN E FALTERMAIER ,  GRUENING ULRIKE ,  RAJARAAO JANMII ,  MANDELMAN JACK A ,  PARKS CHRISTOPHER C ,  PAUL C PARIIZU ,  PAUL A RONSUHAIMU ,  YUN YUU WAN

IPC: B82B1/00 ,  H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain a trench capacitor structure in which mutual influence can be reduced between the regions whose crystallization levels are different. SOLUTION: In a trench capacitor 40, a substrate 60 is provided with a trench 44, an embedded plate electrode 42, a node dielectric 46, an oxide collars 48, trench electrode materials 50, and a conductive type strap 56. A quantum conductive layer which is a silicon nitride thin film is arranged on a boundary face 58 between the conductive strap 56 and the substrate 60 and a boundary face 62 between the trench electrode 50 and the conductive strap 56. The transmission of the recrystallizing force of the trench electrode 50 and the strap 56 to the strap 56 or the substrate 60 can be reduced by this quantum conductive layer. Thus, the reliability of the device can be improved.

公开(公告)号：JP2001044390A

公开(公告)日：2001-02-16

申请号：JP2000209997

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BRONNER GARY ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To obtain non-planar type transistor structure by arranging an active transistor device partially on the sidewall of a deep trench in a cell, and aligning the side wall to a first crystal plane with a crystal orientation along the single- crystal axis. SOLUTION: A deep trench accumulation capacitor 10 is formed in a pad 22 and a substrate 24, and a pattern is formed on the pad 22 using a light lithography step. Then, using such a dry etching step as reactive ion etching, a trench 20 is formed to a desired depth in the substrate 24 through the pad 22. Then, an active transistor device is partially provided on a sidewall 32 of the trench 20, and the sidewall 32 is aligned to first crystal planes (001) and (011) with a crystal orientation set along the single-crystal axis.

公开(公告)号：JP2001044384A

公开(公告)日：2001-02-16

申请号：JP2000220682

申请日：2000-07-21

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  RADENS CARL J ,  TOBBEN DIRK

IPC: H01L27/108 ,  H01L21/76 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce a method for forming an embedded plate diffusion region in a deep trench storage capacitor by filling a non-photosensitive underfill material into the lower region of a trench before forming a collar at the upper region of the trench. SOLUTION: A trench 10 is covered with a thin barrier film 30, and a non- photosensitive underfill 16 is filled into the lower region of the trench 10. Then, the barrier film 30 is eliminated by an upper region 223 of the trench 10 by chemical etching using wet solution or the like. Also, the underfill 16 masks a lower region, 24 while the barrier film 30 at the upper region 22 is being removed. Then, the underfill 16 is removed from a lower region by stripping or the like by a chemical containing HF, and a collar 32 is formed at the upper region 22 by thermal oxidation growth or the like by the local oxidation process.