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    Complementary bipolar inverter
    3.
    发明专利
    Complementary bipolar inverter 未知

    公开(公告)号：GB2505612A

    公开(公告)日：2014-03-05

    申请号：GB201322170

    申请日：2012-04-15

    Applicant: IBM

    Inventor： CAI JIN ,  DENNARD ROBERT HEATH ,  HAENSCH WILFRIED E A ,  NING TAK HUNG

    IPC: H01L21/8228 ,  H01L21/84 ,  H01L27/082 ,  H01L27/12

    Abstract: An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.

    Local interconnect structure self-aligned to gate structure
    4.
    发明专利
    Local interconnect structure self-aligned to gate structure 未知

    公开(公告)号：GB2503176A

    公开(公告)日：2013-12-18

    申请号：GB201317939

    申请日：2012-01-16

    Applicant: IBM

    Inventor： KHAKIFIROOZ ALI ,  CHENG KANGGUO ,  DORIS BRUCE ,  HAENSCH WILFRIED E A ,  HARAN BALASUBRAMANIAN ,  KULKARNI PRANITA

    IPC: H01L21/8244 ,  H01L21/768 ,  H01L21/8234

    Abstract: A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.

    Structure and method to fabricate resistor on finfet processes
    5.
    发明专利
    Structure and method to fabricate resistor on finfet processes 未知

    公开(公告)号：GB2500541A

    公开(公告)日：2013-09-25

    申请号：GB201312090

    申请日：2011-12-21

    Applicant: IBM

    Inventor： HAENSCH WILFRIED E A ,  KULKARNI PRANITA ,  YAMASHITA TENKO

    IPC: H01L21/84 ,  H01L27/12

    Abstract: A structure comprises first and at least second fin structures are formed. Each of the first and at least second fin structures has a vertically oriented semiconductor body. The vertically oriented semiconductor body is comprised of vertical surfaces. A doped region in each of the first and at least second fin structures is comprised of a concentration of dopant ions present in the semiconductor body to form a first resistor and at least a second resistor, and a pair of merged fins formed on outer portions of the doped regions of the first and at least second fin structures. The pair of merged fins is electrically connected so that the first and at least second resistors are electrically connected in parallel with each other.

    Local interconnect structure self-aligned to gate structure
    6.
    发明专利
    Local interconnect structure self-aligned to gate structure 未知

    公开(公告)号：GB2503176B

    公开(公告)日：2014-07-02

    申请号：GB201317939

    申请日：2012-01-16

    Applicant: IBM

    Inventor： KHAKIFIROOZ ALI ,  CHENG KANGGUO ,  DORIS BRUCE ,  HAENSCH WILFRIED E A ,  HARAN BALASUBRAMANIAN ,  KULKARNI PRANITA

    IPC: H01L21/8244 ,  H01L21/768 ,  H01L21/8234

    Abstract: A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.

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