EQUIPMENT AND METHOD FOR PROCESSING SEMICONDUCTOR WAFER AND SIMILAR DEVICE

    公开(公告)号:JPH11251420A

    公开(公告)日:1999-09-17

    申请号:JP36507798

    申请日:1998-12-22

    Applicant: SIEMENS AG IBM

    Abstract: PROBLEM TO BE SOLVED: To substantially prevent abrasions and scratches on the rear side of a wafer from becoming an excessive quantity during wafer processing. SOLUTION: When subsequent wafers 14 are processed subsequently on an electrostatic chuck, warpage of the wafer 14 is decided. The electrostatic chuck 12 clamps the wafer 14 on a clamping face by a clamping force. A controller detects the inherent warpage of the wafer 14 and decides on a minimum clamp voltage to be applied to the electrostatic chuck 12, based on the measured warpage. The voltage is a value decided for each wafer 14, so as to surely clamp the wafer 14 on the clamping face and to eliminate excessive warpage and abrasion on the rear side of the wafer 14. The data of the minimum clamp voltage and the related discriminating part for the wafer 14 for subsequent processing of each wafer 14 are decided and stored, by the use of the measured warpage.

    DAMASCENE MUTUAL CONNECTION WITH IMPROVED RELIABILITY AND ITS MANUFACTURE

    公开(公告)号:JP2000100822A

    公开(公告)日:2000-04-07

    申请号:JP26415999

    申请日:1999-09-17

    Applicant: IBM SIEMENS AG

    Abstract: PROBLEM TO BE SOLVED: To limit the forming quantity of an inter-metallic compound by sticking a wetting layer containing first metal which is brought into contact with an insulator to a recessed part, a uniform barrier layer on it, and a second metallic conduction layer on it at a temperature which is lower than that, at which the inter-metal compound is generated by means of diffusing first and second metals on the barrier layer. SOLUTION: Barrier layers 20 of nonreactive compounds are formed on wetting layers 18, where the metal of titanium(Ti) is evaporated by CVD on the sidewalls of the recessed parts 12 of an insulating layer 10 on the substrate 11 of a silicon water. The barrier layers 20 are formed of an arbitrary material, whose diffusion temperature of the constitution elements of the wetting layers 18 and the metallic layers, is higher than the reaction temperature of the constitution elements, and titanium nitride(TiN) is desirable. It is thicker than the sidewalls of the wetting layers 18 and is more uniform. Then, the recessed parts 12 are completely filled with the conduction layers a metal such as aluminum(Al). In the reaction between Ti of the wetting layers 18 and Al of the conduction layers 22, Ti and Al are unable to diffuse at a temperature lower than 430 deg.C, and they are brought into contact with each other and do not react.

    FORMATION OF METAL FILLING STRUCTURE PART

    公开(公告)号:JP2000049117A

    公开(公告)日:2000-02-18

    申请号:JP16303399

    申请日:1999-06-09

    Applicant: IBM SIEMENS AG

    Abstract: PROBLEM TO BE SOLVED: To provide a technology for filling an opening part, such as a trench and barrier of high-aspect ratio using an economical and reliable method. SOLUTION: An improved method for forming a metal filling structure part at an opening part of a substrate 1 of an integrated circuit device is provided. An intermittent metal liner 18 by CVD is formed at an opening part 100, which is to be filled, provided at a dielectrics layer of the substrate 1. On the intermittent metal liner 18, a metal is further deposited by physical vapor-deposition to form a metal filling structure part. Since the intermittent metal liner provides a wettability equal to or better than that of the intermittent (??) CVD liner, an opening part of an opening width significantly narrower than 250 nm can be filled.

    INTEGRATED CIRCUIT
    9.
    发明专利

    公开(公告)号:JPH11330244A

    公开(公告)日:1999-11-30

    申请号:JP9247299

    申请日:1999-03-31

    Applicant: SIEMENS AG IBM

    Abstract: PROBLEM TO BE SOLVED: To provide an interconnection with a damascene structure having an improved reliability, by using a liner for surrounding or sealing a conductor to give random crystal grain orientation to a conductive material. SOLUTION: A layer 137 is deposited on an insulating layer 130. A layer for lining the wall and the bottom of the contact opening functions as a base coat or liner for a conductive layer 138 to be subsequently deposited to fill the contact opening, and the degree of crystal grain orientation randomness of a material that fills the damascene structure is expanded. A parameter used for depositing a TiN layer is selected to expand the degree of base coat crystal grain orientation randomness and/or amorphous characteristics. The liner has an enough thickness to ensure the random crystal grain orientation of the conductive material to be subsequently deposited. Thus, the interconnection in an IC having the improved reliability can be obtained.

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