公开(公告)号：EP1356498A4

公开(公告)日：2009-05-13

申请号：EP01990114

申请日：2001-12-13

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ENGEL BRETT H ,  HOINKIS MARK ,  MILLER JOHN A ,  SEO SOON-CHEON ,  WANG YUN-YU ,  WONG HON WONG

IPC: H01K3/10 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/50 ,  H01L23/52 ,  H01L23/532 ,  H05K3/02

CPC classification number: H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect (30, 50) and low-k interlayer dielectrics (40), a problem of open circuits after heat treatment was discovered and solved bz the use of a first liner layer of Cr (42), followed by a conformal liner layer of CVD TiN (46), followed in turn bz a final liner layer of Ta or TaN (48), thus improving adhesion between the via (50) and the underlying copper layer (30) while maintianing low resistance.

公开(公告)号：AU2002346512A1

公开(公告)日：2003-07-30

申请号：AU2002346512

申请日：2002-11-22

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K ,  WANG YUN YU ,  KALTALIOGLU ERDEM ,  CHEN TZE-CHIANG ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L29/40 ,  H01L23/48 ,  H01L23/52

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

公开(公告)号：MY134796A

公开(公告)日：2007-12-31

申请号：MYPI20030029

申请日：2003-01-06

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： CHEN TZE-CHIANG ,  WANG YUN YU ,  KALTALIOGLU ERDEM ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A ,  KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

Abstract: AN ADVANCED BACK-END-OF-LINE (BEOL) METALLIZATION STRUCTURE IS DISCLOSED. THE STRUCTURE INCLUDES A BILAYER DIFFUSION BARRIER OR CAP, WHERE THE FIRST CAP LAYER (116, 123) IS FORMED OF A DIELECTRIC MATERIAL PREFERABLY DEPOSITED BY A HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION (HDP CVD) PROCESS, AND THE SECOND CAP LAYER (117, 124) IS FORMED OF A DIELECTRIC MATERIAL PREFERABLY DEPOSITED BY A PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION (PE CVD) PROCESS. A METHOD FOR FORMING THE BEOL METALLIZATION STRUCTURE IS ALSO DISCLOSED. THE INVENTION IS PARTICULARLY USEFUL IN INTERCONNECT STRUCTURES COMPRISING LOW-K DIELECTRIC MATERIAL FOR THE INTER-LAYER DIELECTRIC (ILD) AND COPPER FOR THE CONDUCTORS.

公开(公告)号：EP1470580A4

公开(公告)日：2005-07-20

申请号：EP02784578

申请日：2002-11-22

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES CORP

Inventor： CHEN TZE-CHIANG ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A ,  KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K ,  WANG YUN YU ,  KALTALIOGLU ERDEM

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer (116, 123) is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer (117, 124) is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Abstract translation: 公开了一种先进的后端（BEOL）金属化结构。 该结构包括双层扩散阻挡层或盖，其中第一覆盖层由优选通过高密度等离子体化学气相沉积（HDP CVD）工艺沉积的电介质材料形成，并且第二覆盖层由优选沉积的介电材料形成 通过等离子体增强化学气相沉积（PE CVD）工艺。 还公开了一种用于形成BEOL金属化结构的方法。 本发明在包括用于层间电介质（ILD）的低k电介质材料和用于导体的铜的互连结构中是特别有用的。

公开(公告)号：WO2004053979A8

公开(公告)日：2005-05-12

申请号：PCT/EP0350957

申请日：2003-12-08

Applicant: IBM ,  IBM DEUTSCHLAND ,  INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS JR ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

Abstract translation: 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体（14）被覆盖层（16）和电介质层（18）覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体（14）。 在溅射蚀刻的过程中，将覆盖层再沉积（22）到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

公开(公告)号：EP1756856A4

公开(公告)日：2010-02-17

申请号：EP05755089

申请日：2005-05-31

Applicant: IBM

Inventor： DUNN DERREN N ,  KIM HYUNGJUN ,  ROSSNAGEL STEPHEN M ,  SEO SOON-CHEON

IPC: H01L21/283 ,  H01L21/285 ,  H01L21/4763 ,  H01L21/52 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/28562 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：JP2004336051A

公开(公告)日：2004-11-25

申请号：JP2004136335

申请日：2004-04-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  GRECO STEPHEN E ,  KWIETNIAK KEITH T ,  SEO SOON-CHEON ,  YANG CHIH-CHAO ,  WANG YUN-YU ,  WONG KWONG H

IPC: H01L21/312 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76856 ,  H01L2221/1036

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a wiring layer in an integrated circuit structure.
SOLUTION: An organic insulating layer is formed, the insulating layer is patterned, a liner is accumulated on the insulating layer, the above structure is exposed in plasma, and a pore is formed in an insulating layer of an area adjacent to the liner. The liner is formed sufficiently thin so that plasma penetrates the liner and the pore is formed on the insulating layer without influencing the liner. During the plasma processing, the plasma penetrates the liner without influencing the liner. After the plasma processing, an additional liner can be accumulated. Thereafter, a conductor is accumulated and an excessive portion of the conductor is deleted from the structure. This method produces an integrated circuit structure including the organic insulating layer having a patterned structure, a liner covering the rear side of the patterned structure, and a conductor filling the patterned structure. The insulating layer includes the pore along the surface area of the insulating layer contacting to the liner, and further, the pore is only existent along the surface area contacting to the liner (where the liner is non-existent inside the pore).
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于在集成电路结构中形成布线层的方法。 解决方案：形成有机绝缘层，对绝缘层进行图案化，在绝缘层上积累衬垫，将上述结构暴露在等离子体中，并且在邻近的区域的绝缘层中形成孔 衬垫。 衬垫形成得足够薄，使得等离子体穿透衬垫，并且在绝缘层上形成孔而不影响衬垫。 在等离子体处理期间，等离子体渗透衬垫而不影响衬套。 在等离子体处理之后，可以累积额外的衬垫。 此后，导体被累积，导体的过多部分从结构中删除。 该方法产生包括具有图案化结构的有机绝缘层，覆盖图案化结构的后侧的衬垫和填充图案化结构的导体的集成电路结构。 绝缘层包括沿着与衬垫接触的绝缘层的表面积的孔，此外，孔沿着与衬垫接触的表面区域（其中衬里不存在于孔内）存在。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2013115427A

公开(公告)日：2013-06-10

申请号：JP2012196345

申请日：2012-09-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： THEODORUS EDUARDUS STANDAERT ,  BALASUBRAMANIAN S HARAN ,  CHENG KANGGUO ,  SHOM PONOTH ,  YAMASHITA TENKO ,  SEO SOON-CHEON

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

CPC classification number: H01L29/6681 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a FinFET which is improved in flatness of a gate.SOLUTION: The gate is arranged on a pattern of fins before unnecessary fins are removed. The unnecessary fins can be removed by using a lithography technique, an etching technique, or a combination of them. All or some of the remaining fins can be merged.

Abstract translation: 要解决的问题：提供一种形成FinFET的方法，该FinFET在栅极的平坦度方面得到改善。 解决方案：在不必要的散热片被去除之前，门被布置在鳍状图案上。 可以通过使用光刻技术，蚀刻技术或它们的组合来去除不需要的散热片。 所有或一些剩余的鳍可以合并。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：WO2005122253A3

公开(公告)日：2006-12-14

申请号：PCT/US2005018953

申请日：2005-05-31

Applicant: IBM ,  DUNN DERREN N ,  KIM HYUNGJUN ,  ROSSNAGEL STEPHEN M ,  SEO SOON-CHEON

Inventor： DUNN DERREN N ,  KIM HYUNGJUN ,  ROSSNAGEL STEPHEN M ,  SEO SOON-CHEON

IPC: H01L21/283 ,  H01L21/285 ,  H01L21/4763 ,  H01L21/52 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/28562 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of depositing a tantalum nitride (TaN) diffusion barrier region on low-k materials. The methods include forming a protective layer (104) on the low-k material substrate (102) by performing plasma-enhanced atomic layer deposition (PE-ALD) from tantalum-based precursor and a nitrogen plasma in a chamber. The protective layer (104) has a nitrogen content greater than its tantalum content. A substantially stoichiometric tantalum-nitride layer is then formed by performing PE-ALD from the tantalum-based precursor and a plasma including hydrogen and nitrogen. The invention also includes the tantalum-nitride diffusion barrier region (108) so formed. In one embodiment, the metal precursor includes tantalum penta-chloride (TaC1 5 ). The invention generates a sharp interface between low-k materials and liner materials.

Abstract translation: 在低k材料上沉积氮化钽（TaN）扩散阻挡区域的方法。 所述方法包括通过从钽基前体和室中的氮等离子体进行等离子体增强的原子层沉积（PE-ALD）在低k材料衬底（102）上形成保护层（104）。 保护层（104）的氮含量大于钽的含量。 然后通过从钽基前体和包括氢和氮的等离子体中进行PE-ALD形成基本上化学计量的氮化钽层。 本发明还包括如此形成的氮化钽 - 氮化物扩散阻挡区域（108）。 在一个实施方案中，金属前体包括五氯化钽（TaCl 5 N 5）。 本发明在低k材料和衬垫材料之间产生尖锐的界面。

公开(公告)号：WO2011084666A3

公开(公告)日：2011-10-27

申请号：PCT/US2010060931

申请日：2010-12-17

Applicant: IBM ,  KELLY JAMES J ,  BAKER VEERARAGHAVAN S ,  SEO SOON-CHEON ,  HARAN BALA S ,  VO TUAN A

Inventor： KELLY JAMES J ,  BAKER VEERARAGHAVAN S ,  SEO SOON-CHEON ,  HARAN BALA S ,  VO TUAN A

IPC: H01L21/28

CPC classification number: H01L21/2885 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole (112) can be formed in a dielectric layer (120) to at least partially expose a region (108) including at least one of semiconductor or conductive material. A seed layer (143) can be deposited over a major surface (118) of the dielectric layer and over a surface within the hole (112). In one embodiment, the seed layer (143) can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer (132) consisting essentially of cobalt can be electroplated over the seed layer (143) within the hole (112) to form a contact via (110) in electrically conductive communication with the region.

Abstract translation: 根据本发明的一个方面，提供了一种用于制造具有接触通孔的半导体元件的方法。 在这种方法中，可以在电介质层（120）中形成孔（112）以至少部分地暴露包括半导体或导电材料中的至少一种的区域（108）。 种子层（143）可以沉积在介电层的主表面（118）之上并且在孔（112）内的表面之上。 在一个实施例中，种子层（143）可以包括选自铱，锇，钯，铂，铑和钌的金属。 可以在孔（112）内的种子层（143）上电镀基本上由钴构成的层（132），以形成与该区域导电连通的接触通孔（110）。