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    Ion bombardment method of producing integrated semiconductor circuit resistors of low temperature coefficient of resistance
    3.
    发明授权
    Ion bombardment method of producing integrated semiconductor circuit resistors of low temperature coefficient of resistance 失效
    生产低温系数电阻的集成半导体电路的离子化方法

    公开(公告)号：US3925106A

    公开(公告)日：1975-12-09

    申请号：US42853773

    申请日：1973-12-26

    Applicant: IBM

    Inventor： KU SAN-MEI ,  MASTERS BURTON J

    IPC: H01L27/04 ,  H01L21/00 ,  H01L21/265 ,  H01L21/822 ,  H01L29/66 ,  H01L29/8605 ,  H01L7/44

    CPC classification number: H01L29/8605 ,  H01L21/00 ,  Y10S148/024 ,  Y10S438/934

    Abstract: A method for producing integrated circuit resistors of relatively high resistivity which are temperature stable, i.e., have a low temperature coefficient of resistance at operating temperatures. The resistor is formed in a selected region of an integrated circuit substrate through the introduction of appropriate dopant ions by standard ion implantation or diffusion techniques. However, the concentration of such introduced dopant ions is in excess of the concentration ordinarily required by such techniques. The region into which such dopant ions are introduced is subjected to a bombardment with non-dopant ions at a dose which is sufficient to damage the crystal structure of the region but insufficient to form an amorphous phase in this bombarded region; the bombardment may be carried out either before, after or, where appropriate, even simultaneously with the introduction of the dopant ions. As a result of this ion bombardment, the sheet resistance of the resistor region becomes substantially higher than the selected resistance despite the presence of excess dopant ions. Then, the substrate is heated at a temperature of from 500*C. to 800*C. for a time sufficient to partially anneal the damage so as to lower the sheet resistance of the region to the selected sheet resistance. The annealing time/temperature cycle is carried out so as to maintain the temperature coefficient of resistance below the temperature coefficient of resistance for conventional high resistivity resistors produced by ion implantation or diffusion.

    Method of electrolessly plating alloys
    4.
    发明授权
    Method of electrolessly plating alloys 失效
    无电镀合金的方法

    公开(公告)号：US3890455A

    公开(公告)日：1975-06-17

    申请号：US26594872

    申请日：1972-06-23

    Applicant: IBM

    Inventor： BALLAS DONALD F ,  KU SAN-MEI ,  MARINACE JOHN C

    IPC: C23C18/48 ,  H01L21/288 ,  H01L7/00 ,  B05D5/12

    CPC classification number: H01L21/288 ,  C23C18/48 ,  Y10S148/065

    Abstract: Disclosed is a method of electrolessly plating an alloy onto a substrate. To plate an alloy consisting of two elements requires the steps of mixing two solutions, each containing one of the elements to be alloy plated, and immersing a surface to be plated in said mixed solution for a fixed period of time until a desired thickness of alloy has been plated onto the surface.

    Abstract translation: 公开了将合金无电镀在基板上的方法。 为了镀覆由两种元素组成的合金，需要混合两种溶液的步骤，每种溶液含有要镀合金的元素之一，并将待镀的表面浸入所述混合溶液中一段固定的时间，直到所需的合金厚度 已被镀在表面上。

    7.
    发明专利
    未知

    公开(公告)号：DE2250989A1

    公开(公告)日：1973-05-24

    申请号：DE2250989

    申请日：1972-10-18

    Applicant: IBM

    Inventor： JACOBUS JUN WILLIAM NELSON ,  KU SAN-MEI

    IPC: H01L21/761 ,  H01L21/00 ,  H01L21/22 ,  H01L21/31 ,  H01L21/316 ,  H01L21/331 ,  H01L23/29 ,  H01L27/15 ,  H01L29/73 ,  H01L7/44

    Abstract: 1411555 Matrix displays INTERNATIONAL BUSINESS MACHINES CORP 6 Nov 1972 [19 Nov 1971] 51115/72 Heading G5C [Also in Division H1] A process for forming an array of LEDs in a III-V compound substrate 10 includes covering its surface with an upper layer 14 which is impervious to a diffusant and has windows therein, and an oxide lower layer 12 which is pervious to the diffusant. The layer 12 may be silicon dioxide deposited pyrolytically, and pervious to zinc, magnesium and cadmium dopants. The layer 14 may be silicon nitride, aluminium oxide, phosphosilicate glass or various metals. To improve masking of the layer 14, a further layer 16 of silicon dioxide is deposited over layer 14. Following photo-etching of windows in layers 14, 16, the dopant is diffused into the substrate through the layer 12. The substrate may be of GaAs, GaP, AlAs, BP or a mixed III-V compound, e.g. GaAs x P 1-x , and may be doped with tin, silicon or tellurium to a concentration of 2À10 18 atoms/c.c. Contacts (not shown) are made to the diffused regions via apertures in layer 12, the contacts comprising a gold zinc alloy covered with chromium and gold layers.

    8.
    发明专利
    未知

    公开(公告)号：DE69023951D1

    公开(公告)日：1996-01-18

    申请号：DE69023951

    申请日：1990-03-27

    Applicant: IBM

    Inventor： KU SAN-MEI ,  PERRY KATLEEN ALICE

    IPC: H01L29/73 ,  H01L21/285 ,  H01L21/302 ,  H01L21/331 ,  H01L21/768 ,  H01L29/732 ,  H01L21/311

    Abstract: A method of forming semiconductor device contacts includes the steps of: providing a semiconductor substrate (26) having at least two features e.g. a polysilicon land (36), another polysilicon land (48), and substrate (26),thereon whereat it is desired to make electrical connections; forming a layer (54) of etch stop material having a first etch characteristic over each of the features; forming a layer (56) of dielectric material having a second etch characteristic over each of the features; simultaneously etching at least two vias (58, 66, 60) through the layer of dielectric material using an etchant selective to the layer of dielectric material so as to substantially stop on the layer of etch stop material, the at least two vias including a via over each of the features; and extending the vias through the layer of etch stop material so as to expose the features for subsequent electrical connections (76, 74, 78).

    METHOD OF FORMING RECESSED OXIDE ISOLATION WITH REDUCED STEEPNESS OF THE BIRD'S NECK
    9.
    发明专利
    METHOD OF FORMING RECESSED OXIDE ISOLATION WITH REDUCED STEEPNESS OF THE BIRD'S NECK 未知

    公开(公告)号：CA1226681A

    公开(公告)日：1987-09-08

    申请号：CA504798

    申请日：1986-03-24

    Applicant: IBM

    Inventor： CHRISTIE ROSEMARY ,  HWANG BAO-TAI ,  KU SAN-MEI ,  SICKLER JANET M

    IPC: H01L21/76 ,  H01L21/306 ,  H01L21/308 ,  H01L21/316 ,  H01L21/762 ,  H01L21/72

    Abstract: Disclosed is a method of forming in a monocrystalline silicon body an optimum recessed oxide isolation structure with reduced steepness of the bird's neck. Starting from a monocrystalline silicon body, there is formed thereon a layered structure of first silicon dioxide, polycrystalline silicon, second silicon dioxide and silicon nitride, in that order. The layers are patterned to form openings in the structure at the areas where it is desired to form the oxide isolation pattern within the silicon body. The exposed areas of the silicon body are anisotropically reactive ion etched to an initial portion of the desired depth obtaining the corresponding portion of the trench having substantially vertical walls. Then by chemical etching the trench is extended to a final portion of the desired depth obtaining inwardly sloped walls in the final portion. The body is then thermally oxidized until the desired oxide isolation penetrates to the desired depth within the silicon body.

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