公开(公告)号：JP2008269601A

公开(公告)日：2008-11-06

申请号：JP2008104478

申请日：2008-04-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NGUYEN DUNG QUOC ,  BARARAMU SHINHAROI ,  LE HUNG QUI

IPC: G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3861

Abstract: PROBLEM TO BE SOLVED: To provide a unified register renaming mechanism targeting various instruction types in a microprocessor. SOLUTION: This universal renaming mechanism renames addresses of the various instruction types, using single name structure. An instruction for updating a floating point register (FPR) can be thereby renamed together with an instruction for updating a general purpose register (GPR) or a vector multimedium extension (VMX) instruction register (VR), using the same renaming structure, because the number of states designed for the GPR is same to the number of states designed for the FPR and the GPR. Each address tag (DTAG) is allocated to one address, and a fixed point instruction is allocated to the next DTAG. Considerable amounts of silicon and electric power are saved by providing the single name structure for all the instruction types, in case of the universal renaming mechanism. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种针对微处理器中的各种指令类型的统一的寄存器重命名机制。 解决方案：该通用重命名机制使用单一名称结构重命名各种指令类型的地址。 因此，可以使用相同的重命名结构将用于更新浮点寄存器（FPR）的指令与用于更新通用寄存器（GPR）或向量多媒体扩展（VMX）指令寄存器（VR））的指令一起重命名，因为 为GPR设计的状态数量与为FPR和GPR设计的状态数量相同。 每个地址标签（DTAG）被分配给一个地址，并且固定点指令被分配给下一个DTAG。 在通用重命名机制的情况下，为所有指令类型提供单一名称结构，节省了大量的硅和电力。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008226236A

公开(公告)日：2008-09-25

申请号：JP2008035515

申请日：2008-02-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NGUYEN DUNG QUOC ,  LE HUNG QUI

IPC: G06F15/78 ,  G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/5061 ,  G06F2209/5012

Abstract: PROBLEM TO BE SOLVED: To provide a configurable microprocessor which combines a plurality of corelets into a single microprocessor core to handle high computing-intensive workloads.
SOLUTION: The process for forming the single microprocessor core first selects two or more corelets in the plurality of corelets. The process combines resources of the two or more corelets to form combined resources, wherein each combined resource comprises a larger amount of a resource available to each individual corelet. The process then forms a single microprocessor core from the two or more corelets by assigning the combined resources to the single microprocessor core, wherein the combined resources are dedicated to the single microprocessor core, and wherein the single microprocessor core processes instructions with the dedicated combined resources.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种可配置的微处理器，其将多个核心组合到单个微处理器核心中以处理高计算密集型工作负载。 解决方案：形成单个微处理器核心的过程首先选择多个堆芯中的两个或更多个堆芯。 该过程组合两个或更多个核心小区的资源以形成组合的资源，其中每个组合的资源包括更大量的可用于每个单个小堆的资源。 然后，该过程通过将组合的资源分配给单个微处理器核心而从两个或更多个核心小区形成单个微处理器核心，其中组合资源专用于单个微处理器核心，并且其中单个微处理器核心使用专用组合资源来处理指令 。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JPH10312282A

公开(公告)日：1998-11-24

申请号：JP7372098

申请日：1998-03-23

Applicant: IBM

Inventor： HOICHII CHON ,  LE HUNG QUI ,  JOHN S MYUHIKU ,  WHITE STEVEN W

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To reduce the restriction of instruction completion by permitting a dispatch unit to dispatch an instruction with condition to an appropriate execution unit through a reserved station associated with the execution unit. SOLUTION: In the case of the regular sequence of the instruction or a sequence having the instruction with condition, a take-out unit takes out a sequence 306 waiting for the instruction from an instruction cache 304 based on a prediction sequence. A decoder unit dispatches the instruction to the appropriate execution units (function units) 308-318 through the reserved stations 324-334 associated with the execution units. A branch instruction is dispatched to the branch unit 308, a storage instruction is dispatched to the storage unit 316 and a fixed point instruction containing a lad instruction is dispatched to a 'cluster' unit 314 and the like. Thus, the restriction of instruction completion can be reduced.

公开(公告)号：JPH10283179A

公开(公告)日：1998-10-23

申请号：JP7380398

申请日：1998-03-23

Applicant: IBM

Inventor： JORDAN PAUL J ,  KONIGSBURG BRIAN R ,  LE HUNG QUI ,  WHITE STEVEN W

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a pipeline type data processor for performing the random execution and inference execution of instructions by allocating intrinsic identifiers to the respective instructions and using the identifiers again during the execution of a program inside a data processing system. SOLUTION: This data processing system is provided with an input circuit and a memory for storing plural control values corresponding to the identifiers of plural targets and the memory is provided with first and second banks. Also, a target identification circuit for generating plural target identification values and continuously allocating the respective target identifiers to the corresponding instructions is provided as well. When the target identification values corresponding to the plural control values are allocated inside the first and second banks, the target identification circuit selectively reallocates the first part of the plural target identification values corresponding to the first part of the plural control values inside the first bank. The data processing system 100 is provided with a pipeline type CPU 110 and the CPU 110 is connected to other various constituting elements by a system bus 112.

公开(公告)号：JPH10283187A

公开(公告)日：1998-10-23

申请号：JP10051298

申请日：1998-03-27

Applicant: IBM

Inventor： HOICHII CHON ,  LE HUNG QUI ,  JOHN S MYUHIKU ,  WHITE STEVEN W

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a method for processing interruption and branching recovery unrelated to the type of generated interruption by writing the identification tag to an item inside an architecture register table in the case that the identification tag of a dispatched instruction is the latest one. SOLUTION: The instruction provided with the identification tag and a relating item inside the architecture register table is dispatched, and in the case that the identification tag of the dispatched instruction is newer than the identification tag of a preceding instruction stored in the item, the identification tag is written to the item inside the architecture register table. In this device, a processor 1210 uses an intrinsic instruction identifier and tracks the program order of the instruction dispatched during random execution. In an execution stage, when an operand and execution resources for an indicated operation become usable, execution units 1222, 1228 and 1230 execute the instruction received from a dispatch unit 1220 conveniently.

公开(公告)号：JPH10283180A

公开(公告)日：1998-10-23

申请号：JP7587898

申请日：1998-03-24

Applicant: IBM

Inventor： HOICHII CHON ,  LE HUNG QUI ,  JOHN S MYUHIKU ,  WHITE STEVEN W

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a method for processing interruption and branching recovery unrelated to the type of generated interruption by providing a step for allocating an identification tag to an instruction and the step for dispatching the instruction, the identification tag and source information to an execution queue. SOLUTION: This method is provided with the step for allocating the identification tag to the instruction and the step for dispatching the instruction, the identification tag and the source information to the execution queue. Such a tag system provides an integrated mechanism for supporting complete random execution. For instance, in a processor system, a processor 1210 uses an intrinsic instruction identifier and tracks the program order of the instruction dispatched during random execution. In an execution stage, when an operand and execution resources for an indicated operation become usable, execution units 1222, 1228 and 1230 execute the instruction received from a dispatch unit 1220 conveniently.

公开(公告)号：JP2002287957A

公开(公告)日：2002-10-04

申请号：JP2002042171

申请日：2002-02-19

Applicant: IBM

Inventor： LE HUNG QUI ,  NGUYEN DUNG QUOC

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device adaptable to the temporal request for the high frequency design and accessible to an operand in a single cycle. SOLUTION: An operand buffer having a plurality of entries in which each entry is allocated to the command in generation queues. The operand buffer has the entries of the same number as that of the generation queues. A designed register and a register file for temporary data are input. Data in the operand buffer is written from the register file when the entry is written. When the command is executed, the corresponding entry in the operand buffer is unnecessary, and the entry is dis-allocated. The operand buffer has only entries smaller in number than the register file. Thus, the operand access stage requires the reading of not the register file but the operand buffer, and the operand buffer is read in one cycle.

公开(公告)号：JPH10283181A

公开(公告)日：1998-10-23

申请号：JP7616398

申请日：1998-03-24

Applicant: IBM

Inventor： HOICHII CHON ,  LE HUNG QUI ,  JOHN S MYUHIKU ,  WHITE STEVEN W

IPC: G06F9/38 ,  G06F9/46

Abstract: PROBLEM TO BE SOLVED: To provide a method for processing interruption and branching recovery unrelated to the type of generated interruption by dispatching an instruction and source information to an execution queue, judging the propriety of the source information and issuing the instruction for execution in response to the propriety of the source information. SOLUTION: This method is provided with a step for dispatching the instruction and the source information to the execution queue, the step for judging the propriety of the source information and the step for issuing the instruction for the execution in response to the propriety of the source information. For instance, in a processor system, a processor 1210 uses an intrinsic instruction identifier and tracks the program order of the instruction dispatched during random execution. In an execution stage, when an operand and execution resources for an indicated operation become usable, execution units 1222, 1228 and 1230 execute the instruction received from a dispatch unit 1220 conveniently.

公开(公告)号：GB2502222A

公开(公告)日：2013-11-20

申请号：GB201314787

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  BROWN MARY DOUGLASS ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.

公开(公告)号：GB2494331A

公开(公告)日：2013-03-06

申请号：GB201221747

申请日：2011-05-04

Applicant: IBM

Inventor： HALL RONALD ,  SINHAROY BALARAM ,  LE HUNG QUI ,  SILVERA RAUL ESTEBAN

IPC: G06F9/38 ,  G06F9/30

Abstract: Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.