公开(公告)号：EP2419925A4

公开(公告)日：2016-03-30

申请号：EP10765059

申请日：2010-04-14

Applicant: IBM

Inventor： CHUDZIK MICHAEL P ,  HENSON WILLIAM K ,  JHA RASHMI ,  LIANG YUE ,  RAMACHANDRAN RAVIKUMAR ,  WISE RICHARD S

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/49 ,  H01L29/7833

Abstract: The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.

公开(公告)号：EP2404316A4

公开(公告)日：2016-04-06

申请号：EP10770142

申请日：2010-04-22

Applicant: IBM

Inventor： GREENE BRIAN J ,  CHUDZIK MICHAEL P ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  LIANG YUE ,  MACIEJEWSKI EDWARD P ,  NA MYUNG-HEE ,  NOWAK EDWARD J ,  YU XIAOJUN

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

公开(公告)号：JP2010267964A

公开(公告)日：2010-11-25

申请号：JP2010109553

申请日：2010-05-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YUAN JUN ,  YIN HAIZHOU ,  LIANG YUE ,  YU XIAOJUN ,  FANG SUNFEI ,  CHIDAMBARRAO DURESETI

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L21/28132 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/6659 ,  H01L29/7835 ,  Y10S257/90

Abstract: PROBLEM TO BE SOLVED: To provide an asymmetric semiconductor device, and to provide a method using a spacer scheme in manufacturing the same. SOLUTION: A semiconductor structure is provided that includes an asymmetric gate stack located on a surface of high-k gate dielectric. The asymmetric gate stack includes a first portion and a second portion, wherein the first portion has a different threshold voltage than the second portion. The first portion of the asymmetric gate stack includes, from bottom to top, a threshold voltage adjusting material and at least a first conductive spacer, while the second portion of the asymmetric gate stack includes at least a second conductive spacer over the gate dielectric. In some embodiments, the second conductive spacer is in direct contact with the underlying high-k gate dielectric, while, in other embodiments, the first and second conductive spacers are in direct contact with the threshold voltage adjusting material. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种非对称半导体器件，并提供一种使用间隔方案制造该方法的方法。 解决方案：提供了一种半导体结构，其包括位于高k栅极电介质的表面上的不对称栅极堆叠。 非对称栅极堆叠包括第一部分和第二部分，其中第一部分具有与第二部分不同的阈值电压。 不对称栅极堆叠的第一部分包括从底部到顶部的阈值电压调节材料和至少第一导电间隔物，而非对称栅极堆叠的第二部分包括在栅极电介质上的至少第二导电间隔物。 在一些实施例中，第二导电间隔物与下面的高k栅极电介质直接接触，而在其它实施例中，第一和第二导电间隔物与阈值电压调节材料直接接触。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO2012024037A3

公开(公告)日：2014-03-20

申请号：PCT/US2011043855

申请日：2011-07-13

Applicant: IBM ,  CARTIER EDUARD A ,  LIANG QINGQING ,  LIANG YUE ,  WANG YANFENG

Inventor： CARTIER EDUARD A ,  LIANG QINGQING ,  LIANG YUE ,  WANG YANFENG

IPC: H01L21/336

CPC classification number: H01L29/408 ,  G06F17/5045 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k dielectric metal gate structure includes applying a current to a gate contact of the high-k dielectric metal gate structure to raise a temperature of a metal forming a gate stack. The temperature is raised beyond a Vt shift temperature threshold for providing an on-state.

Abstract translation: 使用高k电介质金属栅Vt移位效应提供可编程场效应晶体管（FET）及其制造方法。 控制高k电介质金属栅极结构中的Vt漂移的方法包括向高k电介质金属栅极结构的栅极接触施加电流以升高形成栅极叠层的金属的温度。 温度升高超过Vt转换温度阈值以提供导通状态。

公开(公告)号：DE112012004134T5

公开(公告)日：2014-06-26

申请号：DE112012004134

申请日：2012-10-26

Applicant: IBM

Inventor： BRODSKY MARY JANE ,  CAI MING ,  GUO DECHAO ,  HENSON WILLIAM K ,  NARASIMHA SHREESH ,  LIANG YUE ,  SONG LIYANG ,  WANG YANFENG ,  YEH CHUN-CHEN

IPC: H01L29/786

Abstract: Eine Struktur beinhaltet ein Substrat; einen Transistor, der über dem Substrat angeordnet ist, wobei der Transistor eine Finne aufweist, die aus Silicium besteht, das mit Kohlenstoff implantiert ist; und eine Schicht eines Gate-Dielektrikums und eine Schicht eines Gate-Metalls, die über einem Abschnitt der Finne liegen, der einen Kanal des Transistors definiert. In der Struktur wird eine Kohlenstoffkonzentration innerhalb der Finne so gewählt, dass eine gewünschte Schwellenspannung des Transistors erreicht wird. Darüber hinaus werden Verfahren zum Fertigen eines FinFET-Transistors offenbart. Zudem wird ein planarer Transistor mit einer mit Kohlenstoff implantierten Wanne offenbart, wobei die Kohlenstoffkonzentration innerhalb der Wanne so gewählt wird, dass eine gewünschte Schwellenspannung des Transistors erreicht wird.

公开(公告)号：SG174853A1

公开(公告)日：2011-11-28

申请号：SG2011057296

申请日：2010-04-22

Applicant: IBM

Inventor： GREENE BRIAN J ,  CHUDZIK MICHAEL P ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  LIANG YUE ,  MACIEJEWSKI EDWARD P ,  NA MYUNG-HEE ,  NOWAK EDWARD J ,  YU XIAOJUN

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

公开(公告)号：DE112011103483T8

公开(公告)日：2013-10-02

申请号：DE112011103483

申请日：2011-07-27

Applicant: IBM

Inventor： WANG XINLIN ,  HENSON WILLIAM K ,  RIM KERN ,  LIANG YUE

IPC: H01L21/336 ,  H01L29/78

公开(公告)号：BRPI1007604A2

公开(公告)日：2016-02-16

申请号：BRPI1007604

申请日：2010-04-22

Applicant: IBM

Inventor： GREENE BRIAN J ,  NOWAK EDWARD J ,  MACIEJEWSKI EDWARD P ,  CHUDZIK MICHAEL P ,  NA MYUNG-HEE ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  YU XIAOJUN ,  LIANG YUE

IPC: H01L21/283 ,  H01L29/49

公开(公告)号：CA2750215A1

公开(公告)日：2010-11-04

申请号：CA2750215

申请日：2010-04-22

Applicant: IBM

Inventor： GREENE BRIAN J ,  CHUDZIK MICHAEL P ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  LIANG YUE ,  MACIEJEWSKI EDWARD P ,  NA MYUNG-HEE ,  NOWAK EDWARD J ,  YU XIAOJUN

IPC: H01L21/71 ,  H01L21/77 ,  H01L27/085 ,  H01L27/098

Abstract: Multiple types of gate stacks (100,..., 600) are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric (30L) is formed on the doped semiconductor well (22, 24). A metal gate layer (42L) is formed in one device area, while the high-k gate dielectric is exposed in other device areas (200, 400, 500, 600). Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer (72L) is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

公开(公告)号：DE112012004134B4

公开(公告)日：2017-09-07

申请号：DE112012004134

申请日：2012-10-26

Applicant: IBM

Inventor： BRODSKY MARY JANE ,  CAI MING ,  GUO DECHAO ,  HENSON WILLIAM K ,  NARASIMHA SHREESH ,  LIANG YUE ,  SONG LIYANG ,  WANG YANFENG ,  YEH CHUN-CHEN

IPC: H01L21/336

Abstract: Verfahren zum Fertigen von Transistoreinheiten, das aufweist: Bereitstellen einer Siliciumschicht, die eine Schicht eines Abschirmoxids aufweist, die auf einer oberen Fläche ausgebildet Ist; Aufbringen einer ersten Maskierungsschicht in einer Weise, dass ein erster Abschnitt der Abschirmoxidschicht unbedeckt bleibt; Implantieren von Kohlenstoff in die Siliciumschicht durch den unbedeckten ersten Abschnitt der Abschirmoxidschicht, um ein erstes mit Kohlenstoff implantiertes Volumen der Siliciumschicht mit einer ersten Kohlenstoffkonzentration auszubilden; Entfernen der ersten Maskierungsschicht; Aufbringen einer zweiten Maskierungsschicht in einer Weise, dass ein zweiter Abschnitt der Abschirmoxidschicht unbedeckt bleibt; Implantieren von Kohlenstoff in die Siliciumschicht durch den unbedeckten zweiten Abschnitt der Abschirmoxidschicht, um ein zweites mit Kohlenstoff implantiertes Volumen der Siliciumschicht auszubilden, das eine zweite Kohlenstoffkonzentration aufweist, die sich von der ersten Kohlenstoffkonzentration unterscheidet; Entfernen der zweiten Maskierungsschicht; und ...