中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.017 seconds)

    IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME
    1.
    发明公开
    IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME 有权
    VERBESSERTE CMOS-DIODEN MIT DOPPELGATE-LEITERN UND VERFAHREN ZU IHRER HERSTELLUNG

    公开(公告)号：EP2020029A4

    公开(公告)日：2009-09-09

    申请号：EP07761243

    申请日：2007-04-25

    Applicant: IBM

    Inventor： ONSONGO DAVID M ,  RAUSCH WERNER ,  YANG HAINING S

    IPC: H01L23/62 ,  H01L21/329 ,  H01L29/739 ,  H01L29/78

    CPC classification number: H01L29/7391 ,  H01L29/66356

    Abstract: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

    Abstract translation: 本发明提供了具有双栅极导体的改进的CMOS二极管结构。 具体而言，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电的第一栅极导体和p型导电的第二栅极导体分别位于衬底之上并且与第一和第二区域相邻。 此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。 在第三区域与第二区域或第一区域之间的这种二极管结构中可以形成具有基础耗尽区的积聚区域，并且这种积聚区域的宽度优选地与第二或第一栅极 导体。

    HALO-FREE NON-RECTIFYING CONTACT ON CHIP WITH HALO SOURCE/DRAIN DIFFUSION
    2.
    发明申请
    HALO-FREE NON-RECTIFYING CONTACT ON CHIP WITH HALO SOURCE/DRAIN DIFFUSION 审中-公开
    通过HALO来源/排水扩散进行HALO-FREE非重新接触

    公开(公告)号：WO0195369A3

    公开(公告)日：2002-05-16

    申请号：PCT/GB0102273

    申请日：2001-05-23

    Applicant: IBM ,  IBM UK

    Inventor： CULP JAMES ,  NAYAK JAWAHAR ,  RAUSCH WERNER ,  SHERONY MELANIE ,  VOLDMAN STEVEN ,  ZAMDMER NOAH

    IPC: H01L27/04 ,  H01L21/822 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861

    CPC classification number: H01L29/4966 ,  H01L29/1083 ,  H01L29/7835

    Abstract: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

    Abstract translation: 半导体芯片包括具有整流接触扩散和非整流接触扩散的半导体衬底。 光晕扩散与整流接触扩散相邻，并且没有晕圈扩散与非整流接触扩散相邻。 整流接触扩散可以是FET的源极/漏极扩散，以提高耐穿透性。 非整流接触扩散可以是FET体接触，横向二极管接触或电阻或电容器接触。 避免使用非整流触点的光圈可以降低串联电阻并提高器件特性。 在具有相邻扩散的光晕的器件的芯片的另一实施例中，没有卤素扩散与横向二极管的整流接触扩散相邻，从而显着地提高了二极管的理想性并增加了击穿电压。

    Cmos well structure and forming method therefor
    4.
    发明专利
    Cmos well structure and forming method therefor 有权
    CMOS微结构及其形成方法

    公开(公告)号：JP2005150731A

    公开(公告)日：2005-06-09

    申请号：JP2004328193

    申请日：2004-11-11

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： JOSHI RAJIV V ,  HSU LOUIS C ,  HOOK TERENCE B ,  RAUSCH WERNER

    IPC: H01L21/76 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78

    CPC classification number: H01L29/78 ,  H01L21/823892 ,  H01L27/0928

    Abstract: PROBLEM TO BE SOLVED: To provide a CMOS well structure and a method for forming it.
    SOLUTION: A method for forming a CMOS well structure comprises a process of forming multiple first conductivity type wells over a substrate. The multiple first conductivity type wells are formed in respective openings in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on the sidewalls of each of the first conductivity type wells. Multiple second conductivity type wells are formed in respective areas between the first conductivity type wells. Multiple shallow trench isolations are formed between the first conductivity type wells and the second conductivity type wells. The multiple first conductivity type wells are formed in a first selective epitaxial growth process, and the multiple second conductivity type wells are formed in a second selective epitaxial growth process.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种CMOS阱结构及其形成方法。 解决方案：用于形成CMOS阱结构的方法包括在衬底上形成多个第一导电类型阱的工艺。 在第一掩模中的相应开口中形成多个第一导电类型的阱。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电型孔的侧壁上形成侧壁间隔物。 在第一导电型孔之间的相应区域中形成多个第二导电类型的阱。 在第一导电类型阱和第二导电类型阱之间形成多个浅沟槽隔离。 在第一选择性外延生长工艺中形成多个第一导电型阱，并且在第二选择性外延生长工艺中形成多个第二导电型阱。 版权所有（C）2005，JPO＆NCIPI

    IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME
    5.
    发明申请
    IMPROVED CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME 审中-公开
    改进的具有双栅导体的CMOS二极管及其形成方法

    公开(公告)号：WO2007127770A3

    公开(公告)日：2008-11-13

    申请号：PCT/US2007067361

    申请日：2007-04-25

    Applicant: IBM ,  ONSONGO DAVID M ,  RAUSCH WERNER ,  YANG HAINING S

    Inventor： ONSONGO DAVID M ,  RAUSCH WERNER ,  YANG HAINING S

    IPC: H01L23/62

    CPC classification number: H01L29/7391 ,  H01L29/66356

    Abstract: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

    Abstract translation: 本发明提供了具有双栅极导体的改进的CMOS二极管结构。 具体地，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电体的第一栅极导体和p型导电体的第二栅极导体分别位于衬底上并且分别邻近第一和第二区域。 此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。 可以在第三区域和第二区域或第一区域之间的这种二极管结构中形成具有底层耗尽区域的积聚区域，并且这样的累积区域优选地具有与第二或第一栅极的宽度正相关的宽度 导体。

    Halo-free non-rectifying contact on chip with halosource/drain diffusion
    8.
    发明专利
    Halo-free non-rectifying contact on chip with halosource/drain diffusion 未知

    公开(公告)号：HK1055508A1

    公开(公告)日：2004-01-09

    申请号：HK03107752

    申请日：2003-10-28

    Applicant: IBM

    Inventor： CULP JAMES ,  NAYAK JAWAHAR ,  RAUSCH WERNER ,  SHERONY MELANIE ,  VOLDMAN STEVEN ,  ZANDMER NOAH

    IPC: H01L21/822 ,  H01L27/04 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L

    Abstract: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

    Halo-free non-rectifying contact on chip with halo source/drain diffusion
    9.
    发明专利
    Halo-free non-rectifying contact on chip with halo source/drain diffusion 未知

    公开(公告)号：AU5859401A

    公开(公告)日：2001-12-17

    申请号：AU5859401

    申请日：2001-05-23

    Applicant: IBM

    Inventor： NAYAK JAWAHAR ,  RAUSCH WERNER ,  SHERONY MELANIE ,  VOLDMAN STEVEN ,  ZAMDMER NOAH

    IPC: H01L27/04 ,  H01L21/822 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861

    Abstract: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

Patent Agency Ranking