公开(公告)号：EP1856735A4

公开(公告)日：2009-07-15

申请号：EP06737610

申请日：2006-03-08

Applicant: IBM ,  SONY CORP

Inventor： NGUYEN SON V ,  LANE SARAH L ,  LINIGER ERIC G ,  IDA KENSAKU ,  RESTAINO DARRYL D

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76801 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A material stack (12) is provided comprising one or more films (14) that have a crack velocity of about IE- 10 m/sec or greater and at least one monolayer (16) within or in direct contact with the one or more films (14), wherein the at least one monolayer (16) reduces the crack velocity of the material stack (12) to a value of less than lE-10 m/sec. The one or more films ( 14) are not limited to low k dielectrics, but may include materials such as a metal. In a preferred embodiment, a low k dielectric stack (12) is provided, having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack (12) are improved by introducing at least one nanolayer (16) into the dielectric stack (12). The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of me films within the stack (12) and without the need of subjecting the inventive dielectric stack (12) to any post treatment steps.

公开(公告)号：EP1849183A4

公开(公告)日：2010-09-01

申请号：EP06735050

申请日：2006-02-14

Applicant: IBM ,  SONY CORP

Inventor： NGUYEN SON V ,  LANE SARAH L ,  LEE JIA ,  IDA KENSAKU ,  RESTAINO DARRYL D ,  NOGAMI TAKESHI

IPC: H01L21/31

CPC classification number: H01L21/7682 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3122 ,  H01L21/31633 ,  H01L2221/1047

公开(公告)号：WO2006096813A2

公开(公告)日：2006-09-14

申请号：PCT/US2006008449

申请日：2006-03-08

Applicant: IBM ,  SONY CORP ,  NGUYEN SON V ,  LANE SARAH L ,  LINIGER ERIC G ,  IDA KENSAKU ,  RESTAINO DARRYL D

Inventor： NGUYEN SON V ,  LANE SARAH L ,  LINIGER ERIC G ,  IDA KENSAKU ,  RESTAINO DARRYL D

IPC: H01L21/469 ,  H01L23/52 ,  H01L23/58

CPC classification number: H01L21/76801 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A material stack (12) is provided comprising one or more films (14) that have a crack velocity of about IE- 10 m/sec or greater and at least one monolayer (16) within or in direct contact with the one or more films (14), wherein the at least one monolayer (16) reduces the crack velocity of the material stack (12) to a value of less than lE-10 m/sec. The one or more films ( 14) are not limited to low k dielectrics, but may include materials such as a metal. In a preferred embodiment, a low k dielectric stack (12) is provided, having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack (12) are improved by introducing at least one nanolayer (16) into the dielectric stack (12). The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of me films within the stack (12) and without the need of subjecting the inventive dielectric stack (12) to any post treatment steps.

Abstract translation: 提供材料堆叠（12），其包括一个或多个膜（14），其具有大约IE-10m / sec或更大的裂纹速度和至少一个单层（16）在一个或多个膜内或直接接触一个或多个膜 （14），其中所述至少一个单层（16）将所述材料堆叠（12）的裂纹速度降低到小于1E-10m / sec的值。 一个或多个膜（14）不限于低k电介质，而是可以包括诸如金属的材料。 在优选实施例中，提供具有约3.0或更小的有效介电常数k的低k电介质堆叠（12），其中通过引入至少一个纳米层（16）来提高堆叠（12）的机械性能 ）到介电叠层（12）中。 在不显着增加叠层（12）内的薄膜的介电常数并且不需要对本发明的电介质叠层（12）进行任何后处理步骤的情况下，实现机械性能的改善。

公开(公告)号：WO2006088881A3

公开(公告)日：2007-01-18

申请号：PCT/US2006005204

申请日：2006-02-14

Applicant: IBM ,  SONY CORP ,  NGUYEN SON V ,  LANE SARAH L ,  LEE JIA ,  IDA KENSAKU ,  RESTAINO DARRYL D ,  NOGAMI TAKESHI

Inventor： NGUYEN SON V ,  LANE SARAH L ,  LEE JIA ,  IDA KENSAKU ,  RESTAINO DARRYL D ,  NOGAMI TAKESHI

IPC: H01L21/31

CPC classification number: H01L21/7682 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3122 ,  H01L21/31633 ,  H01L2221/1047

Abstract: A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter "SiCOH") in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, -CH 2 - crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH 3 +CH 2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH 3 bonding of greater than about 2.0, and a peak area for Si-O-Si bonding of greater than about 60%, and a porosity of greater than about 20%.

Abstract translation: 在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高 键合相互作用，提供比现有技术的SiCOH电介质更多的碳作为甲基端基和更少的亚甲基-CH 2 - 2交联基团。 SiCOH电介质的特征在于具有小于约1.40的CH 3 N 2 CH 2拉伸峰面积的FTIR光谱，SiH拉伸的峰面积小于 约0.20，SiCH 3键的峰面积大于约2.0，Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％ 。

公开(公告)号：JP2004006852A

公开(公告)日：2004-01-08

申请号：JP2003124691

申请日：2003-04-30

Applicant: IBM

Inventor： RESTAINO DARRYL D ,  SIDDIQUI SHAHAB ,  KALTALIOGLU ERDEM ,  BENNETT DELORES ,  LIU C C ,  CHEN HSUEH-CHUNG ,  CHEN TONG-YU ,  YANG GWO-SHII ,  HSIUNG CHIUNG-SHENG

IPC: H01L21/3205 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To reduce via resistance which often occurs at an interface between a liner and the underside of a copper (Cu) layer in a submicron semiconductor integrated circuit using low dielectric constant (low-k) organic ILD materials. SOLUTION: An adhesive catalyst is applied to an upper layer 30, and a silicon dioxide thin film 50 is formed on it by oxidizing the thin film adhesive catalyst before bonding the organic inter-level dielectric substance. In this way, problem is reduced on via resistance in heat cycle of a semiconductor wafer which materializes multilevel metal and organic inter-level dielectric substance. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2000150520A

公开(公告)日：2000-05-30

申请号：JP29239599

申请日：1999-10-14

Applicant: IBM ,  SIEMENS AG

Inventor： CICHY HOLMER U ,  CLAVENGER LAWRENCE A ,  FILIPPI RONALD G ,  IGGULDEN ROY C ,  RESTAINO DARRYL D ,  RODBELL KENNETH P ,  WEBER STEFAN J ,  WEIGAND PETER

IPC: H01L23/52 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/532 ,  H01L27/02

Abstract: PROBLEM TO BE SOLVED: To obtain an interconnection part for an integrated circuit with improved electromigration characteristics. SOLUTION: An interconnection structure part includes titanium lower and upper layers 14 and 20, and the two titanium layers differ from each other in cleanliness. In order to improve electromigration, and to strongly obtain an intermediate layer 18 with texture, the titanium lower layer 14 is not relatively contaminated, and contains a contaminant of at most 5 wt.%. The intermediate layer 18 containing aluminum is formed between the titanium lower and upper layers 14 and 20. The titanium upper layer 20 is relatively more contaminated as compared with the titanium lower layer 14, contains a contaminant of more than 5 wt.%, and contributes to the maintenance of low area resistance.

公开(公告)号：IE20010123A1

公开(公告)日：2001-09-19

申请号：IE20010123

申请日：2001-02-09

Applicant: IBM

Inventor： COHEN STEPHEN ALAN ,  PURUSHOTHAMAN SAMPATH ,  GIGNAC LYNNE M ,  GATES STEPHEN MCCONNELL ,  SIMONYI EVA ,  WILDMAN HORATIO SEYMOUR ,  RESTAINO DARRYL D ,  DALTON TIMOTHY JOSEPH ,  FITZSIMMONS JOHN ANTHONY ,  JAMISON PAUL CHARLES ,  LEE KANG-WOOK

IPC: H01L21/28 ,  H01L21/31 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/223

Abstract: A semiconductor device containing a diffusion barrier layer is provided. The semiconductor device includes at least a semiconductor substrate containing conductive metal elements; and, a diffusion layer applied to at least a portion of the substrate in contact with the conductive metal elements, the diffusion barrier layer having an upper surface and a lower surface and a central portion, and being formed from silicon, carbon, nitrogen and hydrogen with the nitrogen being non-uniformly distributed throughout the diffusion barrier layer. Thus, the nitrogen is more concentrated near the lower and upper surfaces of the diffusion barrier layer as compared to the central portion of the diffusion barrier layer. Methods for making the semiconductor devices are also provided.

公开(公告)号：SG155831A1

公开(公告)日：2009-10-29

申请号：SG2009007931

申请日：2009-02-04

Applicant: CHARTERED SEMICONDUCTOR MFG ,  SAMSUNG ELECTRONICS CO LTD ,  IBM

Inventor： WIDODO JOHNNY ,  HAK KIM JAE ,  BONILLA GRISELDA ,  MOLIS STEVEN E ,  RESTAINO DARRYL D ,  SHOBHA HOSADURGA K

Abstract: Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 A to about 50 A and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water.

公开(公告)号：SG145626A1

公开(公告)日：2008-09-29

申请号：SG2008010068

申请日：2008-02-05

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  SAMSUNG ELECTRONICS CO LTD

Inventor： RESTAINO DARRYL D ,  WIDODO JOHNNY ,  BONILLA GRISELDA ,  DIMITRAKOPOULOS CHRISTOS D ,  GATES STEPHEN M ,  KIM JAE H ,  LANE MICHAEL W ,  LIU XIAO H ,  NGUYEN SON V ,  SHAW THOMAS M

Abstract: BEOL INTERCONNECT STRUCTURES WITH IMPROVED RESISTANCE TO STRESS A chip is provided which includes a back-end-of-line ("BEOL") interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric ("ILD") layers which include a dielectric material curable by ultraviolet ("UV") radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.

公开(公告)号：SG140527A1

公开(公告)日：2008-03-28

申请号：SG2007052699

申请日：2007-07-17

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  SAMSUNG ELECTRONICS CO LTD

Inventor： JAEHAK KIM ,  RESTAINO DARRYL D ,  WIDODO JOHNNY

Abstract: METHODS OF FORMING DUAL-DAMASCENE INTERCONNECT STRUCTURES USING ADHESION LAYERS HAVING HIGH INTERNAL COMPRESSIVE STRESS AND STRUCTURES FORMED THEREBY Methods of forming interconnect structures include forming a first metal wiring pattern on a first dielectric layer and forming a capping layer (e.g., SiCN layer) on the first copper wiring pattern. An adhesion layer is deposited on the capping layer, using a first source gas containing octamethylcyclotetrasilane (OMCTS) at a volumetric flow rate in a range from about 500 sccm to about 700 sccm and a second gas containing helium at a volumetric flow rate in a range from about 1000 to about 3000 sccm. The goal of the deposition step is to achieve an adhesion layer having an internal compressive stress of greater than about 150 MPa therein, so that the adhesion layer is less susceptible to etching/cleaning damage and moisture absorption during back-end processing steps. Additional dielectric and metal layers are then deposited on the adhesion layer. Fig. 2C