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公开(公告)号：DE68901055D1
公开(公告)日：1992-04-30
申请号：DE68901055
申请日：1989-01-27
Applicant: IBM
Inventor： GATES STEPHEN M , LIEHR MICHAEL , RENIER MICHEL G E G , RUBLOFF GARY W
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公开(公告)号：DE69204828D1
公开(公告)日：1995-10-19
申请号：DE69204828
申请日：1992-06-09
Applicant: IBM
Inventor： FORSTER THEODOR , HARDER CHRISTOPH DR , OOSENBRUG ALBERTUS , RUBLOFF GARY W
Abstract: Method for full-wafer processing of laser diodes with cleaved facets combining the advantages of full-wafer processing, to date known from processing lasers with etched facets, with the advantages of cleaved facets. The basic steps of are: 1. defining the position (17) of the facets (18,19) to be cleaved by scribing marks (13) into the top surface of a laser structure comprising epitaxially grown layers, these scribed marks being perpendicular to the optical axis of the lasers to be made, the scribed marks being parallel, their distance (Ic) defining the lenght of the laser cavities and the distance (Ib) between the facets of neighboring laser diodes; 2. covering the uppermost portion of said layers with an etch mask pattern which covers each laser diode to be made such that it extends over the scribed marks of each laser and provides for etch windows between the scribed marks defining the position of facets of neighboring lasers; 3. etching trenches into an upper portion of said laser structure, the shape and location of said trenches being defined by said etch winddows; 4. partly underetching (16) said upper portion during a second etch step such that said laser facets (18,19) can be defined by cleaving said upper portion along said scribed marks (13) without cleaving the whole laser structure; 5. ultrasonically or mechanically cleaving said upper portions being underetched along said scribed marks providing for facets (18,19) being perpendicular to said layers and the optical axis; 6. separating the laser diodes by cleaving them between neighboring lasers.
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公开(公告)号：CA1292965C
公开(公告)日：1991-12-10
申请号：CA507433
申请日：1986-04-24
Applicant: IBM
Inventor： CLABES JOACHIM G , HAHN PETER O , HO PAUL S , LEFAKIS HARALAMBOS , RUBLOFF GARY W
Abstract: Y09-85-014 A technique is described for improving metal-organic substrate adhesion and for reducing stress between the metal film and the substrate. Beams of low energy reactive ions, electrons, or photons are incident upon the substrate to alter the surface chemistry of the substrate to a depth of from about 10 angstroms to a few hundred angstroms. The energy of the incident reactive ions and electrons is about 50-2000eV, while the energy of the incident photons is about 0.2 - 500eV. Irradiation of the substrate can occur prior to or during metal deposition. For simultaneous metal deposition/particle irradiation, the arrival rates of the metal atoms and the substrate treatment particles are within a few order of magnitude of one another. Room temperature or elevated temperatures are suitable.
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Patent Agency Ranking
公开(公告)号：CA1276088C
公开(公告)日：1990-11-13
申请号：CA498399
申请日：1985-12-20
Applicant: IBM
Inventor： HO PAUL S , HAHN PETER O , LEFAKIS HARRY , RUBLOFF GARY W
IPC: C23C14/02 , C23C14/20 , C23C14/58 , H01L21/48 , H01L23/14 , H05K3/14 , H05K3/16 , H05K3/38 , C23C14/34 , B05D3/00 , B05D7/04
Abstract: ENHANCED ADHESION BETWEEN METALS AND POLYMERS A technique is described for increasing the adhesion between metals and organic substrates, where the metals are those which normally only very weakly bond to the substrate. These metals include Ni, Cu, Al, Ag, Au, Ta, Pt, Ir, Rh, Pd, Zn, and Cd. The organic substrates include mylar, polyimides, polyesters, plastics, polyethylene, polystyrene, etc. Enhanced adhesion occurs when intermixing, between the depositing metal atoms and the substrate is optimized to a depth less than about 1000 angstroms into the substrate. This occurs in a critical substrate temperature range of about (0.6-0.8) Tc, where Tc is the curing temperature of the substrate. The deposition rate of the metal atoms is chosen such that the arrival rate of the metal atoms at the surface of the substrate is comparable to or less than the rate of diffusion of metal atoms into the substrate. This provides optimum intermixing and maximum adhesion.
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公开(公告)号：CA1236929A
公开(公告)日：1988-05-17
申请号：CA499662
申请日：1986-01-15
Applicant: IBM
Inventor： BEHA JOHANNES G , DREYFUS RUSSELL W , HARTSTEIN ALLAN M , RUBLOFF GARY W
IPC: G01R31/28 , G01R31/308 , H01L21/66 , G01R31/26
Abstract: PHOTON ASSISTED TUNNELING TESTING OF PASSIVATED INTEGRATED CIRCUITS Covering metal test pads of a passivated integrated circuit process intermediate wafer or completed integrated circuit chip-to-test, with a thin conductive overlayer, and then accessing the test pads through the passivation layer and conductive overlayer, by a pulsed laser to provide voltage-modulated photon-assisted tunneling through the insulation layer, to the conductive overlayer as an electron current, and detecting the resulting electron current, provides a nondestructive test of integrated circuits. The passivation, normally present to protect the integrated circuit, also lowers the threshold for photoelectron emission. The conductive overlayer acts as a photoelectron collector for the detector. A chip-to-test which is properly designed for photon assisted tunneling testing has test sites accessible to laser photons even though passivated. Such a chip-to-test may be nondestructively tested in air at one or several stages of its processing, without the sacrifices of mechanical probing or of bringing test sites out to output pads. The conductive overlayer may be removed after tests have been completed. Integrated circuit process intermediate chips may be specially designed for testability, with test sites grouped for easy access through windows left uncovered by subsequent layers.
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公开(公告)号：CA1220559A
公开(公告)日：1987-04-14
申请号：CA482173
申请日：1985-05-23
Applicant: IBM
Inventor： BEHA JOHANNES G , DREYFUS RUSSELL W , RUBLOFF GARY W
IPC: G01R31/302 , G01R31/308 , H01L21/66 , G01R31/28
Abstract: NONCONTACT DYNAMIC TESTER FOR INTEGRATED CIRCUITS Testing of integrated circuit process intermediates, such as warers, dice or chips in various stages of production (test chips) is facilitated by a nonintrusive, noncontact dynamic testing technique, using a pulsed laser, with laser light modification to increase photon energy through conversion to shorter wavelength. The high energy laser light excites electron emissions to pass to the detection system as a composite function of applied light energy and of dynamic operation of the circuit; detecting those emissions by an adjacent detector requires no ohmic contacts or special circuitry on the integrated circuit chip or wafer. Photoelectron energy emitted from a test pad on the test chip is detected as a composite function of the instantaneous input voltage as processed on the test chip, in dynamic operation including improper operation due to fault. The pulse from the laser, as modified through light modification, the parameters of detection of bias voltages, and the distances involved in chipgrid-detector juxtaposition, provides emissions for detection of circuit voltages occurring on the test chip under dynamic conditions simulating actual or stressed operation, with high time resolution of the voltages and their changes on the circuit. Y0984-020
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公开(公告)号：DE69204828T2
公开(公告)日：1996-05-02
申请号：DE69204828
申请日：1992-06-09
Applicant: IBM
Inventor： FORSTER THEODOR , HARDER CHRISTOPH DR , OOSENBRUG ALBERTUS , RUBLOFF GARY W
Abstract: Method for full-wafer processing of laser diodes with cleaved facets combining the advantages of full-wafer processing, to date known from processing lasers with etched facets, with the advantages of cleaved facets. The basic steps of are: 1. defining the position (17) of the facets (18,19) to be cleaved by scribing marks (13) into the top surface of a laser structure comprising epitaxially grown layers, these scribed marks being perpendicular to the optical axis of the lasers to be made, the scribed marks being parallel, their distance (Ic) defining the lenght of the laser cavities and the distance (Ib) between the facets of neighboring laser diodes; 2. covering the uppermost portion of said layers with an etch mask pattern which covers each laser diode to be made such that it extends over the scribed marks of each laser and provides for etch windows between the scribed marks defining the position of facets of neighboring lasers; 3. etching trenches into an upper portion of said laser structure, the shape and location of said trenches being defined by said etch winddows; 4. partly underetching (16) said upper portion during a second etch step such that said laser facets (18,19) can be defined by cleaving said upper portion along said scribed marks (13) without cleaving the whole laser structure; 5. ultrasonically or mechanically cleaving said upper portions being underetched along said scribed marks providing for facets (18,19) being perpendicular to said layers and the optical axis; 6. separating the laser diodes by cleaving them between neighboring lasers.
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公开(公告)号：CA1232975A
公开(公告)日：1988-02-16
申请号：CA499557
申请日：1986-01-14
Applicant: IBM
Inventor： BEHA JOHANNES G , DREYFUS RUSSELL W , RUBLOFF GARY W
Abstract: NONCONTACT FULL-LINE DYNAMIC AC TESTER FOR INTEGRATED CIRCUITS Simultaneous noncontact testing of voltages across a full line of test sites on an integrated circuit chip-to-test is achieved with high time resolution using photoelectron emission induced by a pulsed laser focussed to a line on the chip-to-test, together with high speed electrostatic deflection perpendicular to the line focus. Photoelectrons produced by the line focus of pulsed laser light are imaged to a line on an array detector, the measured photoelectron intensities at array points along this line representing voltages at corresponding points along the line illuminated by the laser focus. High speed electrostatic deflection applied during the laser pulse, perpendicular to the direction of the line focus, disperses the line image (column) on the array detector across a sequence of sites at right angles (rows), thereby revealing the time-dependence of voltages in the column of test sites with high time resolution (in the picosecond range). Y0984028
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