公开(公告)号：DE3577967D1

公开(公告)日：1990-06-28

申请号：DE3577967

申请日：1985-06-24

Applicant: IBM

Inventor： FEINBERG IRVING ,  KRAUS CHARLES JOHN ,  STOLLER HERBERT IVAN

IPC: H01L25/18 ,  H01L23/538 ,  H01L25/04 ,  H05K1/00 ,  H05K1/03 ,  H05K3/22 ,  H01L23/52 ,  H05K3/46

Abstract: A multiple chip module is provided with an engineering change (EC)/repair facility by means of delete lines (7', 16) located on both major surfaces of the module. In one embodiment, defective pin vias (9') through the module are repaired by use of the delete lines on both major surfaces.

公开(公告)号：DE3577965D1

公开(公告)日：1990-06-28

申请号：DE3577965

申请日：1985-06-11

Applicant: IBM

Inventor： KRAUS CHARLES JOHN ,  STOLLER HERBERT IVAN ,  WU LEON LI-HENG

IPC: H05K3/46 ,  H01L23/538 ,  H05K1/00 ,  H05K1/11 ,  H01L23/52

Abstract: The wiring nets on a module are divided into two groups of planes, i.e., an upper group (5) in which wiring is placed along "north-south" and "east-west" directions and a lower group (6) in which wiring is placed along diagonal directions. All vias (R-vias) for connecting to the wiring pass through the upper group of planes but only half of the vias (D-vias) pass through the lower group of planes. Thus the spacing between the vias of the lower group of planes is greater than the spacing between the upper vias, allowing more lines per wiring channel in the lower group of planes.

公开(公告)号：DE69208415T2

公开(公告)日：1996-09-19

申请号：DE69208415

申请日：1992-09-11

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  INTERRANTE MARIO JOHN ,  KADAKIA SURESH DAMONDARDAS ,  STOLLER HERBERT IVAN ,  MALAVIYA SHASHI DHAR ,  MCLEOD MARK HARRISON ,  RAY SUDIPTA KUMAR

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/538 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40

Abstract: A direct distribution wiring system is provided which facilitates the effecting of repair or engineering change in a Multi-chip module (MCM) while eliminating the need for redistribution and/or buried connections between IC attachment pads and engineering change pads, thus eliminating the need for patterned conductor layers corresponding to such functions. The operation of the MCM is improved by the wiring system allowing the reduction of lumped capacitances by disconnection of defective conductors, accomplished by providing severable connectors in a direct distribution structure, as well as the elimination of redistribution wiring layers and increased IC density on the MCM. Full potential fault coverage as well as full discretion in reversible engineering changes is provided by forming all elements of the wiring system on the surface of the device.

公开(公告)号：DE69208415D1

公开(公告)日：1996-03-28

申请号：DE69208415

申请日：1992-09-11

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  INTERRANTE MARIO JOHN ,  KADAKIA SURESH DAMONDARDAS ,  STOLLER HERBERT IVAN ,  MALAVIYA SHASHI DHAR ,  MCLEOD MARK HARRISON ,  RAY SUDIPTA KUMAR

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/538 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40

Abstract: A direct distribution wiring system is provided which facilitates the effecting of repair or engineering change in a Multi-chip module (MCM) while eliminating the need for redistribution and/or buried connections between IC attachment pads and engineering change pads, thus eliminating the need for patterned conductor layers corresponding to such functions. The operation of the MCM is improved by the wiring system allowing the reduction of lumped capacitances by disconnection of defective conductors, accomplished by providing severable connectors in a direct distribution structure, as well as the elimination of redistribution wiring layers and increased IC density on the MCM. Full potential fault coverage as well as full discretion in reversible engineering changes is provided by forming all elements of the wiring system on the surface of the device.

公开(公告)号：DE3776927D1

公开(公告)日：1992-04-09

申请号：DE3776927

申请日：1987-02-17

Applicant: IBM

Inventor： KRAUS CHARLES JOHN ,  STOLLER HERBERT IVAN ,  WU LEON LI-HENG

IPC: H01L23/538 ,  H01L25/00 ,  H01L25/04 ,  H01L25/18 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H01L23/52

Abstract: A multilayered interposer powering board (2) is disclosed for the distribution of required voltage levels to integrated circuit chip modules (1) under conditions of high current demand and heat induced expansions. The interposer board (2) is introduced between the module (1) and its module mounting board (12). Flexible connector fingers (8, 9) are intermetallically or ohmically connected between a given level of the interposer board and a given power level of the module.

公开(公告)号：DE3065767D1

公开(公告)日：1984-01-05

申请号：DE3065767

申请日：1980-07-10

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  CAVALIERE JOSEPH RICHARD ,  KONIAN RICHARD ROBERT ,  SRINIVASAN GURUMAKONDA ,  STOLLER HERBERT IVAN ,  WALSH JAMES LEO

IPC: H01L21/033 ,  H01L29/08 ,  H01L29/10 ,  H01L21/00

Abstract: A method for making a bipolar filamentary pedestal transistor having reduced base-collector capacitance attributable to the elimination of the extrinsic base-collector junction. Silicon is deposited upon a coplanar oxide-silicon surface in which only the top silicon surface of the buried collector pedestal is exposed through the oxide. Epitaxial silicon deposits only over the exposed pedestal surface while polycrystalline silicon deposits over the oxide surface. The polycrystalline silicon is etched away except in the base region. An emitter is formed in the base region and contacts are made to the emitter, base and collector regions.