公开(公告)号：JP2001068555A

公开(公告)日：2001-03-16

申请号：JP2000210177

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL ,  GABRIEL DANIEL ,  KIRIHATA TOSHIAKI

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02

Abstract: PROBLEM TO BE SOLVED: To combine a laser actuation fuse with an electric starting fuse in order to increase total yield of product. SOLUTION: A plurality of different types of fuses 510, each serving a specified purpose, are arranged on a semiconductor integrated circuit wafer, such that a type of fuse can be actuated without missing the function of different types of fuses. A first type of fuse, e.g. a laser actuation fuse, is principally used for repairing a wafer level defect and a second type of fuse, e.g. an electric starting fuse, is used for repairing a defect found after an IC chip is mounted on a module and a stress is applied to the module during burn-in test. The module level defect is an unit cell trouble corrected normally by an electrically programmed fuse, in order to actuate a module level redundancy arrangement.

公开(公告)号：JP2000353750A

公开(公告)日：2000-12-19

申请号：JP2000144824

申请日：2000-05-17

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BRINTZINGER AXEL ,  KIRIHATA TOSHIAKI ,  NARAYAN CHANDRASEKHAR

IPC: H01L21/82 ,  H01H85/00 ,  H01L23/525 ,  H01H85/044

Abstract: PROBLEM TO BE SOLVED: To array a larger number of fuses densely by electrically connecting at least two fuses that contain a fusing part arrayed in a first level of a multi- layer semiconductor device, respectively. SOLUTION: Each fuse 13 contains a part 15 that is actually fused. The part 15 to be fused is arrayed in a first metal level M1. Like the other part of the fuse 13, the part 15 that is actually fused is made typically of a electrically conductive material, especially aluminum. A termination of each part 15 to be fused is connected to a connector bias 17 that connects that fuse 13 with a connector 19. A gate contact 23 is vertical to a direction of the fuse 13. The gate contact 23 can be connected to a ground that is common to all of existing fuse circuits. Therefore, fuse density is doubled without narrowing the fuse pitch.

公开(公告)号：WO0163648A3

公开(公告)日：2002-04-18

申请号：PCT/US0105373

申请日：2001-02-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  EINSPRUCH FRED L ,  HAFFNER HENNING ,  THOMAS ALAN C

IPC: H01L23/525 ,  G03F1/14

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized narrowed region of the fuse portion at which the electrical fuse is designed to blow. The method then includes providing a photolithography mask substrate and creating on the photolithography mask substrate a fuse mask element adapted to absorb transmission of an energy beam. The fuse mask element has a first mask portion of substantially constant width corresponding to the desired electrical fuse pattern portion of substantially constant width, and a second mask portion corresponding to the localized narrowed region of the fuse portion. The second mask portion comprises either an additional mask element spaced from the first mask portion, a narrowed width portion, or a gap in the first mask portion. The second mask portion is of a configuration sufficient to create a latent image of the electrical fuse pattern, including the localized narrowed region of the fuse portion at which the electrical fuse is designed to blow, upon passing the energy beam through the photolithography mask and onto a resist layer. Preferably, the fuse portion of substantially constant width on the determined fuse pattern has a design width less than about 0.25 mu m, and wherein the localized narrowed region of the fuse portion has a design width less than the design width of the fuse portion.

Abstract translation: 制造用于在半导体结构上形成电熔丝的光刻掩模的方法包括：首先确定用于期望的电熔丝的图案，其中该图案包括除了熔丝部分的局部变窄的区域之外基本恒定宽度的熔丝部分 在此电熔丝被设计为吹塑。 该方法然后包括提供光刻掩模衬底并且在光刻掩模衬底上产生适于吸收能量束的透射的熔丝掩模元件。 熔丝掩模元件具有基本恒定宽度的第一掩模部分和与熔丝部分的局部缩窄区域对应的第二掩模部分，第一掩模部分对应于基本恒定宽度的期望电熔丝图案部分。 第二掩模部分包括与第一掩模部分隔开的另外的掩模元件，变窄的宽度部分或第一掩模部分中的间隙。 第二掩模部分具有足以产生电熔丝图案的潜像的配置，该电图案包括保险丝部分的局部变窄的区域，在电熔丝被设计成在该区域处被吹过，在通过能量束通过光刻掩模并且到 抗蚀剂层。 优选地，在所确定的熔丝图案上具有基本恒定宽度的熔丝部分具有小于约0.25μm的设计宽度，并且其中熔丝部分的局部变窄区域具有小于熔丝部分的设计宽度的设计宽度。

公开(公告)号：WO0118863A9

公开(公告)日：2002-11-07

申请号：PCT/US0024402

申请日：2000-09-06

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： BRINTZINGER AXEL ,  GAMBINO JEFFREY ,  RUPP THOMAS ,  HALLE SCOTT

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In order to form a cavity for a fusible link in a semiconductor device, an etchable material is applied over and around a portion of the fusible link and the etchable material is coated with a protection layer. The access abutting the etchable material is formed through the protection layer. After the removal of the etchable material, the access is partially filled with a refilling material to thereby form the cavity.

Abstract translation: 为了在半导体器件中形成用于可熔连接件的空腔，可蚀刻材料施加在可熔连接件的一部分上和周围，并且可蚀刻材料被涂覆有保护层。 通过保护层形成邻接可蚀刻材料的通路。 在去除可蚀刻材料之后，进入部分地填充有填充材料，从而形成空腔。

公开(公告)号：WO0163648A9

公开(公告)日：2002-10-24

申请号：PCT/US0105373

申请日：2001-02-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  EINSPRUCH FRED L ,  HAFFNER HENNING ,  THOMAS ALAN C

IPC: H01L23/525 ,  G03F1/14

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized narrowed region of the fuse portion at which the electrical fuse is designed to blow. The method then includes providing a photolithography mask substrate and creating on the photolithography mask substrate a fuse mask element adapted to absorb transmission of an energy beam. The fuse mask element has a first mask portion of substantially constant width corresponding to the desired electrical fuse pattern portion of substantially constant width, and a second mask portion corresponding to the localized narrowed region of the fuse portion. The second mask portion comprises either an additional mask element spaced from the first mask portion, a narrowed width portion, or a gap in the first mask portion. The second mask portion is of a configuration sufficient to create a latent image of the electrical fuse pattern, including the localized narrowed region of the fuse portion at which the electrical fuse is designed to blow, upon passing the energy beam through the photolithography mask and onto a resist layer. Preferably, the fuse portion of substantially constant width on the determined fuse pattern has a design width less than about 0.25 mu m, and wherein the localized narrowed region of the fuse portion has a design width less than the design width of the fuse portion.

Abstract translation: 制造用于在半导体结构上形成电熔丝的光刻掩模的方法包括：首先确定所需电熔丝的图案，其中所述图案包括基本恒定宽度的熔丝部分，除了熔丝部分的局部变窄区域 电熔丝被设计在其上。 该方法然后包括提供光刻掩模基板，并在光刻掩模基板上产生适于吸收能量束透射的熔丝屏蔽元件。 熔丝掩模元件具有对应于基本恒定宽度的期望电熔丝图案部分的基本恒定宽度的第一掩模部分和对应于熔丝部分的局部变窄区域的第二掩模部分。 第二掩模部分包括与第一掩模部分间隔开的附加掩模元件，第一掩模部分中的窄宽度部分或间隙。 第二掩模部分具有足以产生电熔丝图案的潜像的构造，包括将电熔丝设计成熔断部分的熔断部分的局部变窄区域，以使能量束通过光刻掩模并进入 抗蚀剂层。 优选地，确定的熔丝图案上的基本上恒定的宽度的熔丝部分具有小于约0.25μm的设计宽度，并且其中熔丝部分的局部变窄区域具有小于熔丝部分的设计宽度的设计宽度。

公开(公告)号：WO0199148A3

公开(公告)日：2002-08-29

申请号：PCT/US0119240

申请日：2001-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： IYER SUNDAR K ,  BRINTZINGER AXEL ,  SMEYS PETER ,  NARAYAN CHANDRASEKHAR ,  IYER SUBRAMANIAN

IPC: H01L23/525 ,  H01L27/102

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse for semiconductor devices, in accordance with the present invention, includes a cathode (104) including a first dopant type, and an anode (102) including a second dopant type where the second dopant type is opposite the first dopant type. A fuse link (106) connects the cathode and the anode and includes the second dopant type. The fuse link and the cathode form a junction (111) therebetween, and the junction is configured to be reverse biased relative to a cathode potential and an anode potential. A conductive layer (103) is formed across the junction such that current flowing at the junction is diverted into the conductive layer to enhance material migration to program the fuse.

Abstract translation: 根据本发明的用于半导体器件的熔断器包括包括第一掺杂剂型的阴极（104）和包括第二掺杂剂类型的阳极（102），其中第二掺杂剂类型与第一掺杂剂类型相反。 熔丝连接（106）连接阴极和阳极并且包括第二掺杂剂类型。 熔丝链和阴极在其间形成结（111），并且该结被配置为相对于阴极电位和阳极电位被反向偏置。 在结上形成导电层（103），使得在结处流动的电流被转移到导电层中以增强材料迁移以对熔丝进行编程。

公开(公告)号：HK1035436A1

公开(公告)日：2001-11-23

申请号：HK01104466

申请日：2001-06-28

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BRINTZINGER AXEL ,  KIEWRA EDWARD W ,  NARAYAN CHANDRASEKHAR ,  RADENS CARL J

IPC: H01L21/82 ,  G11C29/04 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/02 ,  H01L27/108 ,  H01L ,  G11C

Abstract: An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.

公开(公告)号：WO0221594A3

公开(公告)日：2002-05-16

申请号：PCT/US0127135

申请日：2001-08-30

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： BRINTZINGER AXEL

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor chip (100), in accordance with the present invention, includes a substrate (102) and a crack stop structure (300). The crack structure includes a first conductive line (108) disposed over the substrate and at least two first contacts (104) connected to the substrate and to the first conductive line. The at least two first contacts are spaced apart from each other and extend longitudinally along a length of the first conductive line. A second conductive line (112) is disposed over a portion of the first conductive line, and at least two second contacts (116) are connected to the first conductive line and the second conductive line. The at least two second contacts are spaced apart from each other and extend longitudinally along a length of the second conductive line.

Abstract translation: 根据本发明的半导体芯片（100）包括衬底（102）和裂缝停止结构（300）。 该裂缝结构包括设置在衬底上的第一导线（108）和连接到衬底和第一导线的至少两个第一接触件（104）。 所述至少两个第一触头彼此间隔开并且沿所述第一导线的长度纵向延伸。 第二导线（112）设置在第一导线的一部分之上，并且至少两个第二接点（116）连接到第一导线和第二导线。 该至少两个第二触点彼此间隔开并且沿第二导线的长度纵向延伸。

公开(公告)号：WO0215269A3

公开(公告)日：2002-05-10

申请号：PCT/US0123171

申请日：2001-07-23

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LEHMANN GUNTHER ,  BRINTZINGER AXEL

IPC: H01L23/525

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, in accordance with the present invention, includes a plurality of fuses (106) disposed on a same level in a fuse bank (104). A plurality of conductive lines (408) are routed through the fuse bank in between the fuses. A terminal via window (405) is formed in a passivation layer over the plurality of conductive lines and over the plurality of fuses, the terminal via window being formed to expose the fuses in the fuse bank.

Abstract translation: 根据本发明的半导体器件包括设置在保险丝组（104）中的同一电平上的多个保险丝（106）。 多个导线（408）在保险丝之间穿过保险丝库。 端子通孔（405）形成在多个导线上的钝化层中并在多个保险丝上形成，端子通孔被形成为暴露保险丝组中的保险丝。

公开(公告)号：HK1034804A1

公开(公告)日：2001-11-02

申请号：HK01105209

申请日：2001-07-26

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL ,  DANIEL GABRIEL ,  KIRIHATA TOSHIAKI

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02 ,  H01L

Abstract: A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.