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公开(公告)号：US20250120108A1
公开(公告)日：2025-04-10
申请号：US18725965
申请日：2023-11-27
Inventor： Na ZHOU , Junjie LI , Jianfeng GAO , Tao YANG , Junfeng LI , Jun LUO
Abstract: A method for fabricating a GAA nanosheet structure, comprising: forming at least two channel layers and at least one sacrificial layer alternately stacked on a substrate to form a channel stack; forming, on the substrate, a dummy gate astride the channel stack; forming a first sidewall on a surface of the dummy gate; etching the sacrificial layer to form a recess at a side surface of the channel stack; forming a second sidewall within the recess; forming a source and a drain at two sides of the channel stack; in response to a channel layer being in contact with the dummy gate, etching the dummy gate and the channel layer to expose the at least one sacrificial layer, and then etching the at least one sacrificial layer to form a space for manufacturing a surrounding gate; and forming a metallic surrounding gate in the space.
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公开(公告)号：US20230125211A1
公开(公告)日：2023-04-27
申请号：US17942246
申请日：2022-09-12
Inventor： Yan CUI , Jun LUO , Meiyin YANG , Jing XU
Abstract: The present application discloses a spin Hall device, a method for obtaining a Hall voltage, and a max pooling method. The spin Hall device includes a cobalt ferroboron layer. A top view and a bottom view of the spin Hall device are completely the same as a cross-shaped graph that has two axes of symmetry perpendicular to each other and equally divided by each other. The spin Hall device of the present application has non-volatility and analog polymorphic characteristics, can be used for obtaining a Hall voltage and applied to various circuits, is simple in structure and small in size, can save on-chip resources, and can meet computation requirements.
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3.发明申请公开(公告)号：US20200212103A1
公开(公告)日：2020-07-02
申请号：US16411431
申请日：2019-05-14
Inventor： Meiyin YANG , Jun LUO , Tengzhi YANG , Jing XU
Abstract: A spin-orbit torque magnetoresistive random access memory, and a method for manufacturing a spin-orbit torque magnetoresistive random access memory are provided. The spin-orbit torque magnetoresistive random access memory includes a spin-orbit coupling layer and a magnetoresistive tunnel junction located on the spin-orbit coupling layer. The magnetoresistive tunnel junction includes a first magnetic layer, a tunneling layer, and a second magnetic layer that are sequentially stacked from bottom to top, and each of the first magnetic layer and the second magnetic layer has perpendicular anisotropy. In a direction of a current in the spin-orbit coupling layer, defects are generated in a part of the magnetoresistive tunnel junction by an ion implantation process.
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公开(公告)号：US20150325452A1
公开(公告)日：2015-11-12
申请号：US14647393
申请日：2012-12-20
Inventor： Huilong ZHU , Jun LUO , Chunlong LI , Jian DENG , Chao ZHAO
IPC: H01L21/3105 , H01L21/265 , H01L21/321 , H01L29/66 , H01L21/308 , H01L21/311 , H01L29/10
CPC classification number: H01L21/76229 , H01L21/26513 , H01L21/308 , H01L21/31053 , H01L21/31056 , H01L21/31105 , H01L21/32115 , H01L21/32132 , H01L21/823481 , H01L29/1083 , H01L29/66795 , H01L29/6681
Abstract: A planarization process, the process including performing first sputtering on a material layer, with an area of the material layer which has a relatively low loading condition for sputtering shielded by a first shielding layer, removing the first shielding layer, and performing second sputtering on the material layer to planarize the material layer.
Abstract translation: 平面化处理，该方法包括在材料层上进行第一溅射，其中材料层的面积具有相对低的负载条件，用于由第一屏蔽层屏蔽的溅射，去除第一屏蔽层，以及在第二溅射 材料层以平坦化材料层。
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公开(公告)号：US20240371637A1
公开(公告)日：2024-11-07
申请号：US18624334
申请日：2024-04-02
Inventor： Huilong ZHU , Zhuo CHEN , Jinbiao LIU , Junfeng LI , Jun LUO
IPC: H01L21/02 , H01L21/8234 , H01L27/088
Abstract: A method of manufacturing a semiconductor device is provided. The method includes: forming a channel defining layer and a source/drain layer sequentially on a substrate of a crystalline material; patterning the channel defining layer and the source/drain layer as a ridge protruding relative to the substrate; forming a channel layer on a sidewall of the ridge by deposition; and performing a crystallization process to recrystallize the channel layer.
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Patent Agency Ranking
公开(公告)号：US20220231144A1
公开(公告)日：2022-07-21
申请号：US17214042
申请日：2021-03-26
Inventor： Jun LUO , Tianchun YE , Dan ZHANG
IPC: H01L29/423 , H01L29/417 , H01L29/40 , H01L29/06 , H01L29/786 , H01L29/66
Abstract: A semiconductor structure, a method for manufacturing the semiconductor structure, and a transistor. A doped structure is provided, where the doped structure includes a dopant. A surface of the doped structure is oxidized to form the oxide film. In such case, the dopant at an interface between the oxide film and the doped structure may be redistributed, and thereby a segregated-dopant layer is formed inside or at a surface of the doped structure under the oxide film. A concentration of the dopant is higher in the segregated-dopant layer than in other regions of the doped structure. After the oxide film is removed, the doped structure with a high surface doping concentration can be obtained without an additional doping process. Therefore, after a conducting structure is formed on the segregated-dopant layer, a low contact resistance between the conducting structure and the doped structure is obtained, and a device performance is improved.
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公开(公告)号：US20250081530A1
公开(公告)日：2025-03-06
申请号：US18725967
申请日：2023-11-27
Inventor： Junjie LI , Enxu LIU , Na ZHOU , Jianfeng GAO , Junfeng LI , Yongliang LI , Jun LUO , Wenwu WANG
IPC: H01L29/423 , H01L21/3065 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: A semiconductor device and a method for manufacturing the same. The method comprises: providing a substrate; forming a fin, a dummy gate, a first spacer, and a hard mask on a surface of the substrate; etching the substrate to form a groove located directly beneath the fin and running through a second spacer; forming, in the groove, a filling layer made of an insulating dielectric material, and thermal conductivity of the insulating dielectric material is higher than that of the substrate; removing the second spacer through etching; removing two opposite ends of each sacrificial layer to form cavities; filling the cavities to form inner spacers; forming a source and a drain on the substrate; forming a first dielectric layer; planarizing the first dielectric layer to expose the dummy gate; removing the dummy gate to release a channel comprising conductive nanosheets; forming a surrounding gate surrounding the conductive nanosheets.
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8.发明公开公开(公告)号：US20240365534A1
公开(公告)日：2024-10-31
申请号：US18630435
申请日：2024-04-09
Inventor： Huilong ZHU , Tianchun YE , Jun LUO
CPC classification number: H10B12/482 , H10B12/05 , H10B12/485 , H10B12/488 , H10B61/22 , H10N50/10
Abstract: A memory device, including: device layers vertically stacked on a substrate, each device layer including an array of active regions of selection transistors, the array including rows in a first direction and columns in a second direction, the active region including a lower source/drain region, a channel portion, and an upper source/drain region; bit lines arranged in the second direction and extending in the first direction along rows; word line layers vertically stacked and corresponding to the device layers, and each including word lines arranged in the first direction and extending in the second direction to at least partially surround a channel portion in a column of a device layer; sub bit lines extending vertically from each bit line and each electrically connected to a lower source/drain region in a row in each device layer above the bit line; and a memory element electrically connected to the upper source/drain region.
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9.发明公开公开(公告)号：US20240194598A1
公开(公告)日：2024-06-13
申请号：US18532246
申请日：2023-12-07
Inventor： Jianfeng GAO , Weibing LIU , Junjie LI , Na ZHOU , Tao YANG , Junfeng LI , Jun LUO
IPC: H01L23/528 , H01L21/768 , H01L23/522
CPC classification number: H01L23/5283 , H01L21/76802 , H01L21/76834 , H01L21/76843 , H01L21/76877 , H01L23/5226
Abstract: A metal interconnection structure of a semiconductor device and a method for forming the same. The method includes: providing a substrate; forming a first dielectric layer on the substrate; forming a first conductive structure in the first dielectric layer; etching back part of the first conductive structure; forming an etch stop layer on the first conductive structure; forming a second dielectric layer on the etch stop layer and performing chemical mechanical polishing; and forming a second conductive structure in the second dielectric layer, where the second conductive structure is electrically connected to the first conductive structure.
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公开(公告)号：US20180197993A1
公开(公告)日：2018-07-12
申请号：US15849217
申请日：2017-12-20
IPC: H01L29/78 , H01L29/45 , H01L29/167 , H01L29/66 , H01L21/311 , H01L21/265 , H01L21/285 , H01L21/321
CPC classification number: H01L29/7851 , H01L21/26506 , H01L21/26513 , H01L21/28518 , H01L21/76814 , H01L21/76843 , H01L21/76855 , H01L29/456 , H01L29/665 , H01L29/66545 , H01L29/66795
Abstract: The present invention relates to a semiconductor device and a method of manufacturing the same. There is provided a semiconductor device comprising: a semiconductor substrate with a fin; a gate intersecting with the fin and a source region and a drain region within the fin at both sides of the gate; metal silicides formed at the source region and the drain region and in contact with the source region and the drain region respectively; wherein there is a impurity dopant at a interface of the metal silicide in contact with the source/drain region, which is capable of reducing a Schottky barrier height between the metal silicide and the source/drain region. The provided semiconductor device can reduce the Schottky barrier height between the metal silicide and the source/drain region, thereby reducing the specific resistance of the contact.
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