公开(公告)号：JP2003152119A

公开(公告)日：2003-05-23

申请号：JP2002252983

申请日：2002-08-30

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  CASPAR DANIEL ,  FOURNEL RICHARD

IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide an FAMOS memory location which can have at least three completely natural program levels. SOLUTION: An FAMOS memory location is provided with a single floating gate (GR) overlapping the active plane of a semiconductor substrate along contour (PF1, PF2) of at least two asymmetric overlaps in order to determine at least two electrodes in an active region. A memory location program means (MC, SW) applies a set of specified different voltages selectively to the electrodes such that at least three program logical levels are outputted to the memory location.

公开(公告)号：JP2002334589A

公开(公告)日：2002-11-22

申请号：JP2002026723

申请日：2002-02-04

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  AITOUARAB LEILA SEDJAI

IPC: G01R31/28 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/34 ,  G11C29/12 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To prevent a read error caused by variation of a property of a reference memory cell. SOLUTION: This method is a method for refreshing a reference memory cell (Cref) in a non-volatile memory. This method has a step in which the reference cell (Cref) and a test cell (Cveri) are simultaneously selected during read, read signals are compared when a signal read by the reference cell is smaller than a signal read by the test cell, and refresh signals (Sr1, Sr2, Sr3) are outputted to the reference cell (Cref). This method is applied to an electronic memory of a non-volatile type.

公开(公告)号：JP2003273257A

公开(公告)日：2003-09-26

申请号：JP2003057906

申请日：2003-03-05

Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

Inventor： DRAY CYRILLE ,  GENDRIER PHILIPPE ,  FOURNEL RICHARD

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

Abstract: PROBLEM TO BE SOLVED: To provide a memory device which overcomes the data holding problem caused by the thinness of its grid dielectric present in the interface between its STI-type isolation region and its grid material.
SOLUTION: The semiconductor memory device comprises a non-volatile programmable and electrically erasable memory cell having a single layer of grid material. Also, the memory cell comprises a floating grid transistor and a control grid within an active semiconductor area which is formed in a region of a substrate and is delimited by an isolation region. The single layer of grid material wherein the floating grid is formed extends integrally above the active semiconductor area without overlapping part of the isolation region. The floating grid transistor is electrically isolated from the control grid by PN junctions that are inversely polarized.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种克服由其STI型隔离区域和其栅格材料之间的界面中存在的栅极电介质薄度引起的数据保持问题的存储器件。 解决方案：半导体存储器件包括具有单层栅格材料的非易失性可编程和电可擦除存储单元。 此外，存储单元包括浮动栅极晶体管和在有源半导体区域内的控制栅格，该有源半导体区域形成在衬底的区域中并由隔离区域限定。 其中形成浮栅的单层栅格材料在有源半导体区域上整体地延伸，而不与隔离区的重叠部分重叠。 浮栅晶体管通过PN极点与控制栅极电隔离，反向极化。 版权所有（C）2003，JPO

公开(公告)号：JP2003007877A

公开(公告)日：2003-01-10

申请号：JP2002098997

申请日：2002-04-01

Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

Inventor： FOURNEL RICHARD ,  DRAY CYRILLE ,  CASPAR DANIEL

IPC: G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/0416 ,  G11C16/0408

Abstract: PROBLEM TO BE SOLVED: To electrically erase an FAMOS memory cell. SOLUTION: The memory cell is electrically erased by applying a substrate with a voltage VB, having a value less than the threshold predetermined not to break a cell, which is higher at least by 4 volt than a voltage which is the lower of a voltage VS applied to a source and a voltage VD applied to a drain.

Abstract translation: 要解决的问题：电擦除FAMOS存储单元。 解决方案：通过施加具有小于预定值而不破坏电池的电压VB的衬底来电存储存储单元，该电池比电压VS的较低电压至少高4伏 施加到源极和施加到漏极的电压VD。

公开(公告)号：JP2002135970A

公开(公告)日：2002-05-10

申请号：JP2001201430

申请日：2001-07-02

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD

IPC: H02H7/20 ,  G09C1/00 ,  H03K17/10 ,  H03K17/693 ,  H04L9/10

Abstract: PROBLEM TO BE SOLVED: To prevent access to confidential information. SOLUTION: This integrated circuit has a reference ground voltage Gnd and a power supply voltage Vdd for logical operation and is applied with a high voltage HV. It has a protective device 2 that has, at least, one gate oxide circuit element in combination. The protective device 2 is applied with a logical operation voltage Vdd at the power supply node N of, at least, one of the gate oxide circuit elements when operating normally, but the high voltage VH is applied to break down the gate oxide when malfunctioning.

公开(公告)号：FR3037439A1

公开(公告)日：2016-12-16

申请号：FR1555362

申请日：2015-06-12

Applicant: ST MICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： HOTELLIER NICOLAS ,  FOURNEL RICHARD ,  GIANESELLO FREDERIC ,  GUYADER FRANCOIS ,  FIORI VINCENT

IPC: H01L23/18 ,  H01L23/13 ,  H01L23/58

Abstract: Dispositif électronique et procédé de traitement, dans lesquels une plaque arrière (3) comprend une couche arrière de substrat (4), une couche avant de substrat (5) et une couche intermédiaire diélectrique (6), située entre la couche arrière et la couche avant, et comprenant une structure électronique (7) aménagée sur ladite couche avant de substrat (5), incluant des composants électroniques et des moyens de connexion électrique, et dans lesquels ladite couche arrière de substrat (4) présente au moins une région locale pleine (17) et au moins une région locale évidée (18), cette région locale évidée étant aménagée sur toute l'épaisseur de ladite couche arrière, de sorte que ladite couche arrière de substrat ne recouvre pas au moins une zone locale (19) de la face arrière de ladite couche intermédiaire diélectrique (6), correspondant à ladite région locale évidée (18).

公开(公告)号：FR2871282B1

公开(公告)日：2006-09-15

申请号：FR0406077

申请日：2004-06-04

Applicant: ST MICROELECTRONICS SA

Inventor： SCHOELLKOPF JEAN PIERRE ,  FOURNEL RICHARD

IPC: G11C17/08 ,  G11C17/16

Abstract: A one-time programmable, dual-bit memory device comprises one MOS storage transistor having a semiconductor substrate, first and second active regions formed under the surface of the substrate being separated by a part of the substrate forming a channel region, a gate formed on the surface of the said substrate in line with the channel region and whose respective distal ends are aligned with a part of the first active region and with a part of the second active region, respectively, which gate is permanently held at ground potential, and a gate oxide layer running between the gate and the surface of the substrate. The intact or broken down state between the gate and the first active region determines a stored value of a first bit, and the intact or broken down state between the gate and the second active region determines a stored value of a second bit.

公开(公告)号：FR2871282A1

公开(公告)日：2005-12-09

申请号：FR0406077

申请日：2004-06-04

Applicant: ST MICROELECTRONICS SA

Inventor： SCHOELLKOPF JEAN PIERRE ,  FOURNEL RICHARD

IPC: G11C17/08 ,  G11C17/16

Abstract: Un dispositif mémoire à deux bits programmable une seule fois, comprend un transistor MOS de stockage ayant un substrat semiconducteur, une première et une seconde zones actives réalisées sous la surface du substrat en étant séparées par une partie du substrat formant zone de canal, une grille réalisée à la surface dudit substrat au droit de la zone de canal et dont des extrémités distales respectives viennent au droit d'une partie de la première zone active et d'une partie de la seconde zone active respectivement, et portée en permanence à un potentiel de masse, et une couche d'oxyde de grille s'étendant entre la grille et la surface du substrat, dont l'état intact ou claqué entre la grille et la première zone active détermine la valeur stockée d'un premier bit, et dont l'état intact ou claqué entre la grille et la seconde zone active détermine la valeur stockée d'un second bit.

公开(公告)号：FR2849260B1

公开(公告)日：2005-03-11

申请号：FR0216558

申请日：2002-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  VINCENT EMMANUEL ,  BRUYERE SYLVIE ,  CANDELIER PHILIPPE ,  JACQUET FRANCOIS

IPC: G11C14/00 ,  G11C17/14 ,  G11C11/412 ,  G11C11/417

Abstract: The memory cell (10) comprises two inverter circuits (14,16) interconnected between the data nodes (N1,N2) so to form a memory circuit (12), two programming transistors (28,30) for implementing an irreversible degradation of the gate oxide layers of transistors (18,18'), and two transistors (32,34) for implementing the functioning of the memory cell after programming. Each inverter circuit (14,16) comprises supplementary MOS transistors (18,20;18',20') connected in series between a supply voltage source (VDD) and the ground circuit (22). Each inverter circuit comprises a p-MOS transistor (18,18') and an n-MOS transistor (20,20'), and the data nodes (N1,N2) are formed between the two transistors, n-MOS and p-MOS. The degraded MOS transistor is a transistor with thin gate oxide layer (GO1). The oxide layer is degraded at least locally so to obtain a variation of current through the transistor at the time of reading the cell. The programming transistors (28,30), or the diodes, are connected between the programming control line (PROG) and the transistors of the inverter circuits. The n-MOS programming transistors (28,30) ensure a selective connection of the gates of the transistors (18,18') to a programming voltage (VREF) at a level sufficient to cause the degradation of the gate oxide layers of the transistors. The inverter circuits are interconnected by the intermediary of a n-MOS transistor (32,34) connected to the control line (SRAM) of functioning the cell as the SRAM cell. The drain and the source electrodes of the transistors (32,34) are connected to the gates of the transistors of the inverter circuits.

公开(公告)号：FR2838554B1

公开(公告)日：2004-07-09

申请号：FR0209454

申请日：2002-07-25

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  DRAY CYRILLE ,  GENDRIER PHILIPPE

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/02

Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.