公开(公告)号：DE69831921D1

公开(公告)日：2006-03-02

申请号：DE69831921

申请日：1998-12-04

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  SOURGEN LAURENT ,  ZATELLI NICOLA ,  LISART MATHIEU

IPC: G11C16/02 ,  H01L21/8247 ,  H01L23/556 ,  H01L23/58 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

公开(公告)号：JPH11265588A

公开(公告)日：1999-09-28

申请号：JP36090498

申请日：1998-12-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  ZATELLI NICOLA ,  SOURGEN LAURENT ,  LISART MATHIEU

IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To enable the protection of an EEPROM cell which is improved with respect to abnormal readouts by allowing the cell to include floating-gate transistors, a first metallic layer over-lapping with a semiconductor substrate and a second metallic layer positioned by being more separated from the substrate than the first metallic layer and allowing the metallic first layer to be arranged so as to be overlapped in major portions of floating gate terminals. SOLUTION: A metallic structure for a screen 50 is arrayed so as to be overlapped on floating gate terminals 30 and covers only the terminals 30 completely. Since it is advantageous that the metallic structure 50 is formed in a first metallic layer, a selection terminal is provided by a poly silicon structure contacting in the relation that it is oven lapped with a metallic structure 242 formed in the first metallic layer in order to lower the low efficiency of a word line. Moreover, it is advantageous in order to obtain a small-sized cell layout that one side of readout terminals 14, 16 or both terminals are provided by a metallic structure to be formed in a metallic layer succeeding to the first metallic layer, that is, the second metallic layer.

公开(公告)号：JP2001237825A

公开(公告)日：2001-08-31

申请号：JP2000366035

申请日：2000-11-30

Applicant: ST MICROELECTRONICS SA

Inventor： POMET ALAIN ,  PLESSIER BERNARD ,  SOURGEN LAURENT

IPC: H04L9/20 ,  H04L9/00 ,  H04L9/08 ,  H04L9/10

Abstract: PROBLEM TO BE SOLVED: To prevent a data element moving via a bus from being identified or to hardly make the data element identified. SOLUTION: In the electronic component provided with a 2-way bus DATA- BUS through which the data element is moved at a speed of a clock signal PHI between peripheral devices P1, P2, P3 and a central processing unit CPU, each of the central processing unit CPU and at least one peripheral device P1 is provided with a data encryption/decoding cell Kcell employing respectively the same private key KEY, a random signal Kin synchronously with the clock signal PHI is uniquely outputted at each clock cycle of each cell as the current value of the private key and applied to the respective cells through a unidirectional transmission line.

公开(公告)号：DE60030074T2

公开(公告)日：2007-03-29

申请号：DE60030074

申请日：2000-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： POMET ALAIN ,  PLESSIER BERNARD ,  SOURGEN LAURENT

IPC: H04L9/08 ,  H04L9/20 ,  H04L9/00 ,  H04L9/10

Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

公开(公告)号：FR2867286A1

公开(公告)日：2005-09-09

申请号：FR0402161

申请日：2004-03-02

Applicant: ST MICROELECTRONICS SA

Inventor： PISTOULET PIERRE ,  SOURGEN LAURENT

IPC: A61M39/02 ,  G05B19/045 ,  G06K19/073

Abstract: The machine has a flip-flop (31) receiving a following sate code to provide a current state code (CSC) in synchronization with a clock signal. A current state decoder (33) has comparators comparing the code (CSC) and preset codes (SC0-SCk) by full scale decoding to provide identification signals to a NOR gate (35). The gate provides an error signal when the code (CSC) does not correspond to the preset codes having a hamming distance equal to 2. Independent claims are also included for the following: (A) an integrated circuit having state machines (B) a method of manufacturing a state machine of an integrated circuit.

公开(公告)号：DE69700123D1

公开(公告)日：1999-04-08

申请号：DE69700123

申请日：1997-05-05

Applicant: ST MICROELECTRONICS SA

Inventor： LISART MATHIEU ,  SOURGEN LAURENT

IPC: G11C16/12 ,  H03K4/00 ,  G11C16/06

Abstract: The circuit comprises a voltage booster which produces a high DC output. A control circuit uses this to generate a ramped programming voltage. The source of a first P-type load transistor is connected to the output of the voltage booster. Its drain is coupled to a capacitor and by its gate to the control circuit. The high voltage programming output is produced at the transistor drain. The control circuit includes a pulse generator which applies a stepped voltage to the load transistor gate. The capacitor is formed by line of bits in a memory map. The control circuit also comprises a P-type transistor which is mounted in diode configuration and is used to charge the capacitor with a constant current.

公开(公告)号：DE60030074D1

公开(公告)日：2006-09-28

申请号：DE60030074

申请日：2000-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： POMET ALAIN ,  PLESSIER BERNARD ,  SOURGEN LAURENT

IPC: H04L9/08 ,  H04L9/20 ,  H04L9/00 ,  H04L9/10

Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

公开(公告)号：DE69526753D1

公开(公告)日：2002-06-27

申请号：DE69526753

申请日：1995-07-27

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART SYLVIE ,  SOURGEN LAURENT

IPC: G06F21/22 ,  G06F1/00 ,  G06F7/76 ,  G06F21/00 ,  G09C1/00 ,  H01L27/10 ,  G06F12/14 ,  G06F7/00 ,  H01L23/535

Abstract: The method involves using an executable code generator for discriminating between program instructions and program data, and for bit-scrambling the instructions. The resulting code is loaded into a programmable memory connected by the data bus to a controller. Program code is sent in scrambled form over the data bus, and is de-scrambled by a controller (DBR1,RI) for delivery to a processor (UP). A re-writable memory clears data, which is carried on the data bus and scrambles (DBR2,DBR3) data for storage. The data is unscrambled when read from storage. The scrambling algorithms for program code and for data are different.

公开(公告)号：FR2801751B1

公开(公告)日：2002-01-18

申请号：FR9915115

申请日：1999-11-30

Applicant: ST MICROELECTRONICS SA

Inventor： POMET ALAIN ,  PLESSIER BERNARD ,  SOURGEN LAURENT

IPC: H04L9/20 ,  H04L9/00 ,  H04L9/08 ,  H04L9/10

Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

公开(公告)号：DE69508207D1

公开(公告)日：1999-04-15

申请号：DE69508207

申请日：1995-12-14

Applicant: ST MICROELECTRONICS SA

Inventor： LISART MATHIEU ,  SOURGEN LAURENT

IPC: G06F12/14 ,  G06F21/02 ,  G06K17/00

Abstract: The system includes a microprocessor(1), a memory bank(2- 9) containing words(17), a transmission bus(15) for sending data, address and control information between the microprocessor and the memory bank, and an access protection circuit(18). The access protection circuit contains a decision table(18), circuits(19) for addressing the table(18), with the addresses of the memory words. A protection circuit(31-33) which produces a protection signal as a function of a read of the decision table. It allots(14) to certain words to be protected(17) an arrangement of control bits(21) , a circuit(22) to read these control bits at the time (LEC) of reading these words, and a circuit(23-25) to address the decision table as a function of the value of the bits read.