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公开(公告)号：JPH0831122A
公开(公告)日：1996-02-02
申请号：JP12230495
申请日：1995-05-22
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , PISATI VALERIO
Abstract: PURPOSE: To obtain a servo signal processing device which is effectively used by a parallel structure PRML reading apparatus. CONSTITUTION: This device is used in a parallel structure PRML reading apparatus comprising a variable-gain input amplifier 21, a low-pass analog filter 22, a transversal continuous-time analog filter 23 and a couple of individual parallel processing channels 24, 34 sandwiched between the transversal analog filter 23 and RLL-NRZ decoder 25. Two processing channels 24, 34 are respectively provided with analog-digital converters 26, 36 and subsequent viterbi detectors 27, 37 and are operated depending on alternate sampling systems. The servo signal processing device 30 is provided with a rectifier 31 and an integrator 32 connected to the analog digital converters 26, 36.
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公开(公告)号：JP2001291049A
公开(公告)日：2001-10-19
申请号：JP2001052695
申请日：2001-02-27
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , CAZZANIGA MARCO , VENCA ALESSANDRO
Abstract: PROBLEM TO BE SOLVED: To provide a low supply voltage analog multiplier for supplying an extremely low supply voltage and improving the linearity of input while keeping a sufficient speed by performing the cascade connection of plural stages. SOLUTION: A pair of differential cells 10 and 11 are provided and the respective differential cells are provided with a pair of bipolar transistors 2, 3, 6 and 7 whose emitters are connected to each other. The first transistors 2 and 6 of the respective cells 10 and 11 receive input signals IN+ and IN- at the base terminals and the collector terminals are connected to a first reference voltage Vcc through bias members 4 and 8. The second transistors 3 and 7 of the respective cells are diode constitution and the cells are mutually connected at a common node A corresponding to the base terminals of the second transistors 3 and 7 of the respective pairs.
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3.发明专利
公开(公告)号：JPH11249708A
公开(公告)日：1999-09-17
申请号：JP36474598
申请日：1998-12-22
Applicant: ST MICROELECTRONICS SRL
Inventor： PORTALURI SALVATORE , PISATI VALERIO
Abstract: PROBLEM TO BE SOLVED: To provide a feed forward(FF) circuit structure with which delay can be programmed according to a request while maintaining the suitable band width of signals. SOLUTION: This FF circuit structure provided with programmable zero is provided with first and second cells to be cascade connected. The said first and second cells are respectively provided with the first and second pairs of bipolar transistors, a first high impedance element, a second high element and a fifth transistor 8. The base terminal of the fifth transistor 8 receives a signal, which is outputted from the collector terminal of the first pair of first transistors 1, to be outputted as a positive code at the first cell but to be outputted as a negative code at the second cell in order to determine a transmission function having a pair of special points in molecules. A second transistor 2 in the said pair of first and second transistors 1 and 2 is controlled by respective third and fourth current sources 11 and 9 having different values.
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4.发明专利
公开(公告)号：JP2001285027A
公开(公告)日：2001-10-12
申请号：JP2001040561
申请日：2001-02-16
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , PORTALURI SALVATORE , CAZZANIGA MARCO , CASTELLO RINALDO
Abstract: PROBLEM TO BE SOLVED: To obtain a feedforward type circuit structure, having programmable zero which composes a time-continual filter, a delaychain, etc. SOLUTION: A couple of amplification cells (14, 15) are connected to each other at a node A and connected between a 1st signal (Vin) input IN of a 1st cell 14 and an output terminal U of a 2nd cell 15, and each cell is equipped with a couple of transistors (10, 2; 6, 7) which have a common conduction terminal and other conduction terminals coupled with a 1st voltage reference Vcc through respective bias members. Furthermore, a node X of the 1st cell 14 is connected to the output terminal U and a transistor 8 has a control terminal connected to a node X of the 1st cell 14, a 1st conduction terminal connected to an output terminal U, and a 2nd conduction terminal coupled with a 2nd voltage reference GND through a capacitor Cc. The transistor 8 is equipped with a circuit leg 13.
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公开(公告)号：JP2001274657A
公开(公告)日：2001-10-05
申请号：JP2001031150
申请日：2001-02-07
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , ROSSI AUGUSTO , BETTI GIORGIO , CAZZANIGA MARCO
Abstract: PROBLEM TO BE SOLVED: To provide an FIR filter design that has a structure and a functional feature suitable for processing a signal whose spectrum is not known in advance and executes Hilbert transform so as to eliminate limitations and overcome defects of the design of a conventional technology. SOLUTION: This invention relates to a time continuous FIR(finite impulse response) filter that executes the Hilbert transform. The filter is provided with a delay cell connected in cascade between an input terminal and an output terminal of the filter and with a programmable time delay(Td) for a programmable filter cell having fixed filter coefficients (c0,..., cn). Furthermore, this invention also relates to a filtering method to use the structure of the Hilbert FIR filter to process a signal produced by reading data from a magnetic storage medium adopting the vertical recording.
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Patent Agency Ranking
公开(公告)号：JP2642902B2
公开(公告)日：1997-08-20
申请号：JP12230495
申请日：1995-05-22
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , PISATI VALERIO
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公开(公告)号：JPH0879006A
公开(公告)日：1996-03-22
申请号：JP20722395
申请日：1995-08-14
Applicant: ST MICROELECTRONICS SRL
Inventor： BRIANTI FRANCESCO , ALINI ROBERTO , PISATI VALERIO , GADDUCCI PAOLO
IPC: H03H11/04
Abstract: PROBLEM TO BE SOLVED: To constitute a fourth cell which operates with a low supply power, does not require any floating capacitance, and has a low capacitance load at its input terminal. SOLUTION: A high-pass filter constituted of a current generating circuit 29 which is particularly used for high frequencies, has at least each one of input terminal IN and output terminal OUT, between which a transfer function (Fdt) is formed, incorporates serially arranged transconductance stages 2-5, is connected between a pair of stages 2 and 3 of a fourth cell 18 and a reference voltage (GND), and generates variable currents iK1 and iK2 . The circuit 29 makes the introduction of a programmable zero to the transfer function (Fdt) of the filter 20 possible.
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公开(公告)号：JPH0865064A
公开(公告)日：1996-03-08
申请号：JP19561095
申请日：1995-07-31
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , ALINI ROBERTO , CASTELLO RINALDO , VAI GIANFRANCO
Abstract: PROBLEM TO BE SOLVED: To control the gain of integrator with built-in transconductor by changing the output resistance of active load. SOLUTION: This device comprises a transconductance stage 3 having two input terminals I1 and I2 at least and two output terminals O1 and O2 at least and provided with an active load 4 connected to the output terminals O1 and O2 on the transconductance stage 3 and control circuit 5 for active load 4 connected between the output terminals O1 and O2 and the active load 4.
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公开(公告)号：JPH06196948A
公开(公告)日：1994-07-15
申请号：JP21157793
申请日：1993-08-26
Applicant: ST MICROELECTRONICS SRL
Inventor： CASTELLO RINALDO , ALINI ROBERTO , REZZI FRANCESCO , PISATI VALERIO
Abstract: PURPOSE: To provide a mutual conductor stage for dealing with a high frequency signal. CONSTITUTION: A mutual conductor stage 1 has signal input parts A and B and signal output parts U1 and U2 and is provided with a pair of FET (M1 and M2 ) sharing gates G1 and G2 and sources S1 and S2 , and its output is composed of a pair of bipolar transistors Q1 and Q2 connected to these FET M1 and M2 .
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公开(公告)号：DE69530838D1
公开(公告)日：2003-06-26
申请号：DE69530838
申请日：1995-06-30
Applicant: ST MICROELECTRONICS SRL
Inventor： GADDUCCI PAOLO , MOLONEY DAVID , BRIANTI FRANCESCO , PISATI VALERIO
IPC: G06F7/02
Abstract: The invention relates to a basic cell (11) for comparing a first and a second digital signal (A, B), of the type having at least a first and a second input (I1, I2) and a first and a second output (O3, O4) and comprising at least one logic gate (14) receiving digital signals (A, B) at a first and a second signal input (IS1, IS2), and which comprises at least a first and a second controlled switch (P1, P2) inserted in parallel with each other between the output terminal of the logic gate (14) and the second output (O4) from the cell (11), the first switch (P1) being also connected between the first input (I1) and the first output (O3) of the cell (11) and the second switch (P2) being also connected between the second input (I2) and the second output (O4) of the cell (11). The invention also relates to a digital comparator (9) comprising a plurality of basic cells according to the invention.
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