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    Architecture for reconfigurable digital signal processor
    2.
    发明公开
    Architecture for reconfigurable digital signal processor 审中-公开
    建筑师建筑师Digecignalprozessor

    公开(公告)号：EP1443418A1

    公开(公告)日：2004-08-04

    申请号：EP03425055.5

    申请日：2003-01-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campi, Fabio ,  Toma, Mario ,  Lodi, Andrea ,  Cappelli, Andrea ,  Canegallo, Roberto ,  Guerrieri, Roberto

    IPC: G06F15/78 ,  G06F9/38

    CPC classification number: G06F9/3885 ,  G06F9/3877 ,  G06F9/3897 ,  G06F15/7867

    Abstract: The present invention relates to digital embedded architecture (1), including a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor (2), structured to implement a Very Long Instruction Word elaboration mode by a general purpose hardwired computational logic, and an additional data elaboration channel (5, 6) comprising a reconfigurable function unit based on a pipelined array (7) of configurable look-up table based cells controlled by a special purpose control unit (8), thus easing the elaboration of critical kernels algorithms.

    Abstract translation: 本发明涉及一种数字嵌入式架构（1），包括微控制器和存储器件，适用于数字信号处理中的可重新配置的计算，包括：处理器（2），其被构造为通过一般的实现非常长的指令字精炼模式 以及包括基于由专用控制单元（8）控制的基于可配置的查找表的单元的流水线阵列（7）的可重新配置功能单元（5,6）的附加数据精细化通道（5,6），从而缓解 阐述关键内核算法。

    Method for controlled erasing memory devices, in particular analog and multi-level flash-EEPROM devices
    4.
    发明公开
    Method for controlled erasing memory devices, in particular analog and multi-level flash-EEPROM devices 失效
    用于受控擦除存储器设备，尤其是模拟或值-闪速EEPROM阵列的方法

    公开(公告)号：EP0932161A1

    公开(公告)日：1999-07-28

    申请号：EP98830024.0

    申请日：1998-01-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pasotti, Marco ,  Canegallo, Roberto ,  Chioffi, Ernestina ,  Guaitini, Giovanni ,  Lhermet, Frank ,  Rolandi, Pierluigi

    IPC: G11C16/00 ,  G11C16/06

    CPC classification number: G11C16/3409 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5635 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445 ,  G11C27/005

    Abstract: The controlled erase method includes supplying (40) at least one erase pulse to cells (3) of a memory array (2); comparing (53) the threshold voltage of the erased cells with a low threshold value; selectively soft-programming (62) the erased cells which have a threshold voltage lower than the low threshold value; and verifying (42) whether the erased cells have a threshold voltage lower than a high threshold value, which is higher than the low threshold value. If at least one predetermined number of erased cells has a threshold voltage which is higher than the high threshold value, an erase pulse is applied (44) to all the cells and the steps of comparing, selectively soft-programming and verifying are repeated.

    Abstract translation: 受控擦除方法包括提供（40）至少一个擦除脉冲到单元的存储器阵列的（3）（2）; 比较（53）所述擦除单元具有低阈值的阈值电压; 选择性地软编程（62）的擦除单元，其具有阈值电压低于低阈值低; 和验证（42）是否擦除单元具有阈值电压高于高阈值的情况下，所有这是比所述低阈值高。 如果擦除单元中的至少一个预定数量的具有阈值电压的所有比该高阈值时，以擦除脉冲施加（44）到所有的细胞和进行比较的步骤，选择性地软编程，并且重复验证。

    Communication cell for an integrated circuit, chip comprising the communication cell, electronic system including the chip, and test apparatus
    5.
    发明公开
    Communication cell for an integrated circuit, chip comprising the communication cell, electronic system including the chip, and test apparatus 有权
    用于与通信单元的集成电路芯片通信小区，与所述芯片和测试装置的电子系统

    公开(公告)号：EP2341626A3

    公开(公告)日：2011-08-10

    申请号：EP10197444.2

    申请日：2010-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Canegallo, Roberto ,  Cardu, Roberto ,  Scandiuzzo, Mauro ,  Cani, Salvatore Valerio ,  Perugini, Luca

    IPC: H03K19/0175 ,  G01R31/312

    CPC classification number: H03K19/0175 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2924/01021 ,  H01L2924/13091

    Abstract: A communication cell (20, 60) for enabling data communication between an integrated circuit (7) and an electronic unit (5) distinct from the integrated circuit, comprising a contact pad unit (53; 73), configured for capacitively coupling, in a first operating condition of said communication cell, to the electronic unit for receiving an input signal (S IN ) from said electronic unit, and for ohmically coupling, in a second operating condition of said communication cell, to the electronic unit for receiving the input signal; a receiver device (22), including signal-amplifying means (32, 34), connected between said contact pad unit and said integrated circuit, configured for receiving the input signal and generating an intermediate signal (S C ) correlated to the input signal; signal-selection means (24) receiving the intermediate signal (S C ), the input signal (S IN ), and providing an output signal (S IN ; S C ) which is the intermediate signal (S C ) during the first operating condition, and the input signal (S IN ) during the second operating condition; and an input stage (6), connectable between the integrated circuit and the output terminal (24d) of the signal-selection means, configured for receiving the output signal (S IN ; S C ) and providing the output signal to the integrated circuit.

    Chip-to-chip communication system
    6.
    发明公开
    Chip-to-chip communication system 有权
    芯片到芯片通信系统

    公开(公告)号：EP1762943A8

    公开(公告)日：2007-10-10

    申请号：EP05019644.3

    申请日：2005-09-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ciccarelli, Luca ,  Magagni, Luca ,  Fazzi, Alberto ,  Canegallo, Roberto ,  Guerrieri, Roberto

    IPC: G06F13/40

    CPC classification number: H01L25/0657 ,  G06F13/4077 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: The invention relates to a chip-to-chip communication system (10) of the type comprising at least a transmitter TX (11) and a receiver RX (12), inserted between a first and a second voltage references (Vdd, GND) and connected to respective transmitter and receiver clock terminal wherein respective transmitter and receiver clock signals (CP, G) are applied, the transmitter TX (11) having an input terminal (TXin) receiving an input data (D) and an output terminal (TXout) connected to an input terminal (RXin) of the receiver RX (12) at a connection block (15), the receiver RX (12) having an output terminal (RXout) issuing an output signal (Q).
    Advantageously according to the invention:
    - the transmitter TX (11) comprises at least a precharge and an evaluation blocks (18, 19) connected to each other and to the transmitter clock terminal (CP);
    - the receiver RX (12) comprises at least a precharge block (25) connected to the receiver clock terminal (G)

    the precharge blocks (18, 25) precharging the output terminal (TXout) of the transmitter TX (11) and the input terminal (RXin) of the receiver RX (12), respectively, to a value corresponding to a first voltage reference (Vcc) during a low phase of the transmitter clock signal (CP).

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