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    Single supply voltage nonvolatile memory device with hierarchical row decoding
    3.
    发明公开
    Single supply voltage nonvolatile memory device with hierarchical row decoding 有权
    Einzige SpeisespannungsschaltungfürnichtflüchtigenSpeicher mit hierarchicalischem Reihendekodierer

    公开(公告)号：EP1073060A1

    公开(公告)日：2001-01-31

    申请号：EP99830483.6

    申请日：1999-07-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Khouri, Osama ,  Sacco, Andrea ,  Picca, Massimiliano

    IPC: G11C8/00

    CPC classification number: G11C5/145 ,  G11C5/14 ,  G11C8/10

    Abstract: The memory device (10) comprises a memory array (2) having an organisation of the type comprising global word lines (4) and local word lines (6), a global row decoder (8) addressing the global word lines (4), a local row decoder (12) addressing the local word lines (6), a global power supply stage (22) supplying the global row decoder (8), and a local power supply stage (24) supplying the local row decoder (12).

    Abstract translation: 存储器件（10）包括具有包括全局字线（4）和本地字线（6）类型的组织的存储器阵列（2），寻址全局字线（4）的全局行解码器（8） 寻址本地字线（6）的本地行解码器（12），提供全局行解码器（8）的全局电源级（22）和提供本地行解码器（12）的本地电源级（24） 。

    Voltage regulating circuit for a capacitive load
    4.
    发明公开
    Voltage regulating circuit for a capacitive load 有权
    Spannungsreglerfüreine kapazitive最后

    公开(公告)号：EP1065580A1

    公开(公告)日：2001-01-03

    申请号：EP99830418.2

    申请日：1999-06-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Micheloni, Rino ,  Motta, Ilaria ,  Torelli, Guido

    IPC: G05F3/02 ,  G05F1/56 ,  G05F3/26 ,  H02J7/16

    CPC classification number: G05F3/242

    Abstract: A voltage regulating circuit for a capacitive load, being connected between first and second terminals of a supply voltage generator (VDD,GND) and having an input terminal (IN) and an output terminal (OUT), comprises an operational amplifier (OP) having an inverting (-) input terminal connected to the input terminal (IN) of the regulating circuit and a non-inverting (+) input terminal connected to an intermediate node of a voltage divider (R1,R2) which is connected between an output node connected to the output terminal (OUT) of the regulating circuit and the second terminal (GND) of the supply voltage generator, and having an output terminal connected, for driving a first field-effect transistor (MPU), between the output node and the first terminal (VDD) of the supply voltage generator, the output terminal of the operational amplifier being further connected to the output node through a compensation network (COMP), and comprises a second field-effect transistor (MPD1) connected between the output node and the second terminal of the supply voltage generator (GND) and having its gate terminal connected to a constant voltage generating circuit means (RB,CB,MB,IB).

    Abstract translation: 一种用于电容性负载的电压调节电路，连接在电源电压发生器（VDD，GND）的第一和第二端子之间并具有输入端（IN）和输出端（OUT），包括运算放大器（OP），其具有 连接到调节电路的输入端子（IN）的反相（ - ）输入端子和连接到分压器（R1，R2）的中间节点的非反相（+）输入端子，其连接在输出节点 连接到调节电路的输出端子（OUT）和电源电压发生器的第二端子（GND），并且具有用于驱动第一场效应晶体管（MPU）的输出端子连接在输出节点和 电源电压发生器的第一端子（VDD），运算放大器的输出端子通过补偿网络（COMP）进一步连接到输出节点，并且包括一个与之相连的第二场效应晶体管（MPD1） 在电源电压发生器（GND）的输出节点和第二端子上，并且其栅极端子连接到恒定电压发生电路装置（RB，CB，MB，IB）。

    Electronic memory device having high integration density non volatile memory cells and a reduced capacitive coupling
    5.
    发明公开
    Electronic memory device having high integration density non volatile memory cells and a reduced capacitive coupling 有权
    电子存储装置，其包括具有高集成度和降低的电容耦合的非易失性存储器单元

    公开(公告)号：EP1672646A1

    公开(公告)日：2006-06-21

    申请号：EP05027286.3

    申请日：2005-12-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Caimi, Carlo ,  Mastrodomenico, Giovanni

    IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521 ,  G11C16/0483 ,  H01L27/115

    Abstract: Flash NAND memory electronic device comprising non-volatile cells and having a high integration density and relative programming method. Memory device (1) of the type integrated on a semiconductor substrate (3) and comprising one matrix (6) with rows or Word lines (4) and columns or Bit lines (5) organised in sectors (7) of memory cells (2). The device (1) comprising between said cells (2) of said opposite Word lines (4) belonging to at least one of said sectors (7) of said matrix (6) a lateral coating (15) along the direction of the Bit lines (5) having at least one conductive layer (16) with a contact terminal (9) being selectively biased or floating during each program, read or erase operation, each cell belonging to said sector (7).

    Abstract translation: 闪速NAND存储器的电子设备，其包括非易失性单元和具有高的集成密度和相对编程方法。 存储器设备（1）集成在一个半导体衬底（3），并包括一种基质的类型（6）的行或字线（4）和列线或位线（5）中的存储单元的扇区（7）主办（2 ）。 的装置（1）所述的细胞（2）所述的相对的字线（4）沿着所述位线的方向属于所述扇区（7）。所述的基质（6）的横向涂层中的至少一个（15）之间，其包括 （5）具有与接触端子（9）被选择性偏置或每个节目期间浮动至少一个导电层（16），读取或擦除操作中，每个小区属于所述扇区（7）。

    Low power charge pump circuit
    7.
    发明公开
    Low power charge pump circuit 有权
    Leungung Ladungspumpeschaltung mit niedriger

    公开(公告)号：EP1310959A1

    公开(公告)日：2003-05-14

    申请号：EP01830695.1

    申请日：2001-11-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Soltesz, Dario ,  Pierin, Andrea ,  Torrelli, Guido

    IPC: G11C5/14 ,  H02M3/07

    CPC classification number: G11C5/145 ,  H02M3/073 ,  H02M2001/0032 ,  H02M2003/075 ,  H02M2003/077 ,  Y02B70/16

    Abstract: A charge pump circuit, connected between a first voltage reference and an output terminal, comprises at least two stages consisting of an elementary charge pump circuit connected between said first voltage reference and said output terminal, and adjustment circuitry connected between said output terminal and respective control terminals of said at least two stages. This circuitry is arranged to select for actuation an appropriate combination of these elementary stages according to the current absorbed from a load connected to the output terminal.

    Abstract translation: 连接在第一参考电压和输出端子之间的电荷泵电路包括由连接在所述第一电压基准和所述输出端子之间的基本电荷泵电路和连接在所述输出端子和相应控制器之间的调节电路组成的至少两级 所述至少两个阶段的终端。 该电路被设置为根据从连接到输出端子的负载吸收的电流来选择这些基本级的适当组合。

    A/D conversion method in high density multilevel non-volatile memory devices and corresponding converter device
    8.
    发明公开
    A/D conversion method in high density multilevel non-volatile memory devices and corresponding converter device 有权
    在非易失性更通常高密度存储器和相关联的换能器为模拟/数字转换的方法

    公开(公告)号：EP1211812A2

    公开(公告)日：2002-06-05

    申请号：EP00127649.2

    申请日：2000-11-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Khouri, Osama ,  Pierin, Andrea ,  Gregori, Stefano ,  Torelli, Guido

    IPC: H03M1/14

    CPC classification number: G11C11/56 ,  G11C27/005 ,  H03M1/146 ,  H03M1/361

    Abstract: The invention relates to an analog-to-digital conversion method and relevant device, in high-density multilevel non-volatile memory devices. The method applies to multilevel memory cells comprising a floating gate transistor with drain and source terminals; the cell to be read is subjected to a reading operation by applying predetermined bias voltage values to its drain and source terminals, while to its drain terminal is applied a predetermined current value (Iref), and by measuring the value of its gate voltage (Vg).
    The method of the invention comprises a first conversion phase the most significant bits (MSB) contained in the memory cell, followed by a second conversion phase of the least significant bits (LSB).
    The first step is completed within a time gap (T1-T0) which corresponds to the rise transient of the gate voltage signal (Vg), while the second step is started at the end of the transient.

    Abstract translation: 本发明涉及到模拟 - 数字转换方法和相关的设备，在高密度的多级非易失性存储器装置。 该方法适用于多级存储器单元包括具有漏极和源极端子的浮栅晶体管; 要读出的单元是通过，施加预定的偏置电压值到它的漏极和源极端，而其漏极端子施加规定的电流值（Iref的）经受读取操作，并通过测量其栅极电压的值（Vg的 ）。 本发明的方法包括包含在所述存储器单元中的最显著位（MSB）的第一转化阶段，接着是至少显著位的第二阶段的转换（LSB）。 第一个步骤是一个时间间隙（T1-T0），其对应于栅极电压信号（VG）的上升瞬变内完成，而第二个步骤是在瞬变结束启动。

    Electronic memory device having high density non volatile memory cells and a reduced capacitive interference cell-to-cell
    10.
    发明公开
    Electronic memory device having high density non volatile memory cells and a reduced capacitive interference cell-to-cell 有权
    电子存储装置，包括非易失性存储器单元具有高密度和减小电容的细胞 - 细胞干扰

    公开(公告)号：EP1672645A1

    公开(公告)日：2006-06-21

    申请号：EP05027285.5

    申请日：2005-12-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Khouri, Osama ,  Caimi, Carlo ,  Mastrodomenico, Giovanni ,  Caprara, Paolo

    IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521 ,  G11C16/0483 ,  H01L27/115

    Abstract: Electronic memory device with non-volatile memory cells, high density and reduced interference cell-to-cell, of the type integrated on a semiconductor substrate (3) and organised in matrix with rows or Word lines (4) and columns or Bit lines (5) of memory cells (2). Each of said cells (2) comprises at least one floating gate transistor having a floating gate region (9) projecting from said substrate (3) and a control gate region (12) capacitively coupled to said floating gate region (9). Between the cells (2) of said opposite Word lines (4) a lateral coating (15) is provided comprising at least one conductive layer (16) floating along the direction of said Bit lines (5).

    Abstract translation: 具有非易失性存储器单元，高密度和减小的干扰细胞至细胞，集成在一个半导体衬底（3）和组织在一个矩阵的行或字线（4）和列线或位线（所述类型的电子存储器设备 存储器单元5）（2）。 每个所述电池（2）包括至少一个浮动具有（9），从电容性耦合到所述浮栅区域，在所述基片（3）和控制栅极区域（12）突出的浮栅区栅极晶体管（9）。 将细胞（2）之间的所述相对的字线（4）的横向的涂层（15）设置的至少一个包括用导电层（16）沿所述位线的方向浮动的（5）。

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