Abstract:
The invention relates to an architecture for distributing supply voltages to a plurality of memory modules (Mod1, ..., ModN) supplied through a plurality of charge pump circuits (Pump1, ..., PumpM). Advantageously according to the invention, the architecture for distributing supply voltages comprises a sorting block (11) bidirectionally-connected to the plurality of memory modules (Mod1, ..., ModN) from which it receives a plurality of power requests and it is capable of providing a sorting signal (ORD) of said power requests on the basis of a priority scale in order to drive the plurality of charge pump circuits (Pump1, , PumpM) and distribute convenient supply voltages (Vhigh1, ..., VhighN; Vneg1, ..., VnegN) to the plurality of memory modules (Mod1, ..., ModN). Moreover, this architecture is software-configurable.
Abstract:
The invention relates to a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels (N), which method comprises the phases of:
initially programming (I) a cell threshold value (VthDATI) to a first set of levels [O;(m-1)] being (m) a submultiple of the plurality (N) of levels of the multilevel cell; reprogramming without erasing (II) another set of levels [m;(2m-1)] containing the same number of levels (m) as the first set; reiterating (N R - 1 times) the reprogramming without erasing phase (III,IV, ...) until the levels (N) of the multilevel cell are exhausted.
The invention makes also reference to a multilevel memory device of the type comprising a plurality. of multilevel memory cells organised into sectors, the sectors being themselves split into a plurality of data units (UD) wherein a data updating operation is performed in parallel, the data units (UD) being programmed by means of the programming method according to the invention.
Abstract:
The electronic device (1) is integrated in a chip (50) of semiconductor material, and comprises a control unit (3), a signal-conversion unit (4), and a non-volatile memory unit (5), which are connected together via a main transmission line (6). The signal-conversion unit (4) is designed to receive at input an analog signal correlated to a voice signal, and to generate at output a stream of appropriately compressed digital signals. The stream of compressed digital signals is then stored in pre-set memory locations of the non-volatile memory unit (5) according to the control signals generated by the control unit (3). During reproduction, the compressed digital signals stored in the non-volatile memory unit (5) are supplied to the signal-conversion unit (4), which decompresses them and sends them to a loudspeaker (43).
Abstract:
The controlled erase method includes supplying (40) at least one erase pulse to cells (3) of a memory array (2); comparing (53) the threshold voltage of the erased cells with a low threshold value; selectively soft-programming (62) the erased cells which have a threshold voltage lower than the low threshold value; and verifying (42) whether the erased cells have a threshold voltage lower than a high threshold value, which is higher than the low threshold value. If at least one predetermined number of erased cells has a threshold voltage which is higher than the high threshold value, an erase pulse is applied (44) to all the cells and the steps of comparing, selectively soft-programming and verifying are repeated.
Abstract:
The present invention relates to a 8Mb application-specific embeddable flash memory. It comprises three content-specific I/O ports and delivers a peak read throughput of 1.2GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit, a programming rate of 1 Mbyte/s for non-volatile storage of code, data and embedded FPGA bit stream configurations. The test chip has been designed using a NOR type 0.18µm flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35µm 2 .
Abstract:
An electrically-modifiable, non-volatile, semiconductor memory comprising a plurality of user memory locations which can be addressed individually from outside the memory in order to read and to modify user memory location, there is a corresponding pair of physical memory locations ((X1, Y1), (X2, Y2); WORDn) in the memory, which assume, alternatively, the functions of an active memory location and of a non-active memory location, the active memory location containing a previously-written datum and the non-active memory location being available for the writing of a new datum to replace the previously-written datum, so that, upon a request to replace the previous datum with the new datum, the previous datum is kept in the memory until the new datum has been written.