公开(公告)号：EP1435621A1

公开(公告)日：2004-07-07

申请号：EP02425809.7

申请日：2002-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  De Sandre, Guido ,  Iezzi, David ,  Muzzi, Gilberto ,  Poles, Marco

IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07

CPC classification number: G11C16/30 ,  G06F1/26 ,  G11C5/145

Abstract: The invention relates to an architecture for distributing supply voltages to a plurality of memory modules (Mod1, ..., ModN) supplied through a plurality of charge pump circuits (Pump1, ..., PumpM).
Advantageously according to the invention, the architecture for distributing supply voltages comprises a sorting block (11) bidirectionally-connected to the plurality of memory modules (Mod1, ..., ModN) from which it receives a plurality of power requests and it is capable of providing a sorting signal (ORD) of said power requests on the basis of a priority scale in order to drive the plurality of charge pump circuits (Pump1, , PumpM) and distribute convenient supply voltages (Vhigh1, ..., VhighN; Vneg1, ..., VnegN) to the plurality of memory modules (Mod1, ..., ModN). Moreover, this architecture is software-configurable.

Abstract translation: 本发明涉及一种用于向通过多个电荷泵电路（Pump1，...，PumpM）提供的多个存储器模块（Mod1，...，ModN）分配电源电压的架构。 有利地，根据本发明，用于分配电源电压的架构包括双向连接到多个存储器模块（Mod1，...，ModN）的分类块（11），从该存储器模块接收多个电力请求 并且能够基于优先级来提供所述功率请求的分类信号（ORD），以驱动多个电荷泵电路（Pump1，PumpM）并且分配方便的电源电压（Vhigh1，...） ，VhighN; Vneg1，...，VnegN）连接到多个存储器模块（Mod1，...，ModN）。 而且，这种架构是软件可配置的。

公开(公告)号：EP1139210B1

公开(公告)日：2004-03-17

申请号：EP00830228.3

申请日：2000-03-28

Applicant: STMicroelectronics S.r.l.

Inventor： Rocchi, Alessandro ,  Bisio, Marco ,  Pasotti, Marco ,  Rolandi, Pier Luigi

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7211

公开(公告)号：EP1215679A1

公开(公告)日：2002-06-19

申请号：EP01129768.6

申请日：2001-12-13

Applicant: STMicroelectronics S.r.l.

Inventor： De Sandre, Guido ,  Pasotti, Marco ,  Rolandi, Pier Luigi ,  Guaitini, Giovani ,  Iezzi, David ,  Poles, Marco

IPC: G11C11/56

CPC classification number: G11C11/5635 ,  G11C11/5621 ,  G11C11/5628 ,  G11C17/146

Abstract: The invention relates to a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels (N), which method comprises the phases of:

initially programming (I) a cell threshold value (VthDATI) to a first set of levels [O;(m-1)] being (m) a submultiple of the plurality (N) of levels of the multilevel cell;
reprogramming without erasing (II) another set of levels [m;(2m-1)] containing the same number of levels (m) as the first set;
reiterating (N R - 1 times) the reprogramming without erasing phase (III,IV, ...) until the levels (N) of the multilevel cell are exhausted.

The invention makes also reference to a multilevel memory device of the type comprising a plurality. of multilevel memory cells organised into sectors, the sectors being themselves split into a plurality of data units (UD) wherein a data updating operation is performed in parallel, the data units (UD) being programmed by means of the programming method according to the invention.

Abstract translation: 本发明涉及一种能够存储多个级别（N）中的多个位的多级存储器单元的编程方法，该方法包括以下阶段：首先将单元阈值（VthDATI）编程（I）到第一 层级ÄO;（m-1）Ü是（m）多级单元的多（N）个级别中的一个子; 重新编程而不擦除（II）另一组水平Äm;（2m-1）Ü包含与第一组相同数量的水平（m）; 重复（NR-1次）重编程而不擦除相位（III，IV，...），直到多级单元的电平（N）耗尽。 本发明还涉及包括多个类型的多级存储器件。 的多级存储器单元被组织成扇区，扇区本身被分成多个数据单元（UD），其中并行执行数据更新操作，数据单元（UD）通过根据本发明的编程方法进行编程 。

公开(公告)号：EP1126466A1

公开(公告)日：2001-08-22

申请号：EP00830115.2

申请日：2000-02-18

Applicant: STMicroelectronics S.r.l.

Inventor： Borgatti, Michele ,  Rocchi, Alessandro ,  Bisio, Marco ,  Rolandi, Pierluigi ,  Pasotti, Marco

IPC: G11C7/16 ,  G06F12/02 ,  G06F3/16

CPC classification number: G11C7/16 ,  G06F3/16 ,  G06F12/023 ,  G11B20/00007 ,  G11B20/10527 ,  G11B2020/10685

Abstract: The electronic device (1) is integrated in a chip (50) of semiconductor material, and comprises a control unit (3), a signal-conversion unit (4), and a non-volatile memory unit (5), which are connected together via a main transmission line (6). The signal-conversion unit (4) is designed to receive at input an analog signal correlated to a voice signal, and to generate at output a stream of appropriately compressed digital signals. The stream of compressed digital signals is then stored in pre-set memory locations of the non-volatile memory unit (5) according to the control signals generated by the control unit (3). During reproduction, the compressed digital signals stored in the non-volatile memory unit (5) are supplied to the signal-conversion unit (4), which decompresses them and sends them to a loudspeaker (43).

Abstract translation: 所述电子设备（1）集成在半导体材料的芯片（50），并且包括一个控制单元（3），信号转换单元（4），和非易失性存储器单元（5），其连接 一起经由主传输线（6）。 所述信号转换单元（4）被设计为接收在输入到相关的语音信号的模拟信号，并在输出端适当地产生压缩的数字信号流。 然后被压缩的数字信号的数据流被存储在非易失性存储器单元（5）的预设置的存储器位置雅丁到由控制单元产生的控制信号（3）。 在再现期间，存储在所述非易失性存储器单元（5）的压缩数字信号被提供给信号转换单元（4），该解压缩它们，并将它们发送到扬声器（43）。

公开(公告)号：EP0932161A1

公开(公告)日：1999-07-28

申请号：EP98830024.0

申请日：1998-01-22

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  Canegallo, Roberto ,  Chioffi, Ernestina ,  Guaitini, Giovanni ,  Lhermet, Frank ,  Rolandi, Pierluigi

IPC: G11C16/00 ,  G11C16/06

CPC classification number: G11C16/3409 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5635 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445 ,  G11C27/005

Abstract: The controlled erase method includes supplying (40) at least one erase pulse to cells (3) of a memory array (2); comparing (53) the threshold voltage of the erased cells with a low threshold value; selectively soft-programming (62) the erased cells which have a threshold voltage lower than the low threshold value; and verifying (42) whether the erased cells have a threshold voltage lower than a high threshold value, which is higher than the low threshold value. If at least one predetermined number of erased cells has a threshold voltage which is higher than the high threshold value, an erase pulse is applied (44) to all the cells and the steps of comparing, selectively soft-programming and verifying are repeated.

Abstract translation: 受控擦除方法包括提供（40）至少一个擦除脉冲到单元的存储器阵列的（3）（2）; 比较（53）所述擦除单元具有低阈值的阈值电压; 选择性地软编程（62）的擦除单元，其具有阈值电压低于低阈值低; 和验证（42）是否擦除单元具有阈值电压高于高阈值的情况下，所有这是比所述低阈值高。 如果擦除单元中的至少一个预定数量的具有阈值电压的所有比该高阈值时，以擦除脉冲施加（44）到所有的细胞和进行比较的步骤，选择性地软编程，并且重复验证。

公开(公告)号：EP0913835B1

公开(公告)日：2007-03-21

申请号：EP97830550.6

申请日：1997-10-28

Applicant: STMicroelectronics S.r.l.

Inventor： Canegallo, Roberto ,  Chioffi, Ernestina ,  Pasotti, Marco ,  Gerna, Danilo ,  Rolandi, Pier Luigi

IPC: G11C16/06

CPC classification number: G11C16/3459 ,  G11C16/3454

公开(公告)号：EP1065668B1

公开(公告)日：2006-08-09

申请号：EP99830381.2

申请日：1999-06-21

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  Guaitini, Giovanni ,  Rolandi, Pier Luigi

IPC: G11C16/08 ,  G11C8/00

CPC classification number: G11C8/10 ,  G11C16/08

公开(公告)号：EP0997912B1

公开(公告)日：2006-01-11

申请号：EP98830626.2

申请日：1998-10-20

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  Canegallo, Roberto ,  Guaitini, Giovanni ,  Rolandi, Pier Luigi

IPC: G11C27/00 ,  G11C16/06 ,  G11C11/56

CPC classification number: G11C16/34 ,  G11C7/16 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/26 ,  G11C27/005 ,  G11C2211/5642

公开(公告)号：EP1443519A1

公开(公告)日：2004-08-04

申请号：EP03425057.1

申请日：2003-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  Borgatti, Michele ,  Rolandi, Pier Luigi

IPC: G11C5/14 ,  G11C16/30

CPC classification number: G11C16/30

Abstract: The present invention relates to a 8Mb application-specific embeddable flash memory. It comprises three content-specific I/O ports and delivers a peak read throughput of 1.2GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit, a programming rate of 1 Mbyte/s for non-volatile storage of code, data and embedded FPGA bit stream configurations. The test chip has been designed using a NOR type 0.18µm flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35µm 2 .

Abstract translation: 本发明涉及一种8Mb的特定应用可嵌入闪存。 它包括三项具体内容的I / O端口，并提供1.2GB的/ s的峰值读取吞吐量。 该存储器与一个特殊的自动编程栅电压斜坡发生器电路，1兆字节/秒的代码，数据的非易失性存储和嵌入式FPGA比特流结构的编程速率组合。 测试芯片已使用NOR型快闪嵌入式12时18分微米技术与1.8V电源，二聚设计，六个金属和存储器的12:35微米细胞大小<2>。

公开(公告)号：EP1220229A1

公开(公告)日：2002-07-03

申请号：EP00830878.5

申请日：2000-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Gastaldi, Roberto ,  Lo Giudice, Gianbattista ,  Pasotti, Marco ,  Pio, Federico

IPC: G11C16/10

CPC classification number: G11C16/102

Abstract: An electrically-modifiable, non-volatile, semiconductor memory comprising a plurality of user memory locations which can be addressed individually from outside the memory in order to read and to modify user memory location, there is a corresponding pair of physical memory locations ((X1, Y1), (X2, Y2); WORDn) in the memory, which assume, alternatively, the functions of an active memory location and of a non-active memory location, the active memory location containing a previously-written datum and the non-active memory location being available for the writing of a new datum to replace the previously-written datum, so that, upon a request to replace the previous datum with the new datum, the previous datum is kept in the memory until the new datum has been written.

Abstract translation: 的电可修改，非易失性半导体存储器包括可以单独地被寻址的存储器外，以便读取和修改用户的存储位置的用户存储器位置的复数，有一对相应的物理存储器位置（（X1 ，Y1），（X2，Y2）;在所述存储器中，其中假设，WORDn）可选地，有源存储器位置和一个非活性的存储器位置的功能，活性存储器位置包含先前写入的日期和非 -active存储单元是可用于新的日期的书面替换先前写的日期，使得在更换以前的日期与新日期的请求，先前的日期是保存在内存，直到新的日期有 被写入。