公开(公告)号：JP2000330790A

公开(公告)日：2000-11-30

申请号：JP2000134618

申请日：2000-05-08

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  FEL BRUNO ,  DUCOUSSO LAURENT

IPC: G06F9/30 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To process the data dependency between different instructions by making ineffective a dependency check between instructions in the left-right direction as to instructions of very long instruction word(VLIW) mode. SOLUTION: Instructions are held in a program memory 11, sent to a control unit 12, and supplied to parallel execution pipelines 13 to 16. An instruction is decoded by a decoder 82 and the output of a dependency check circuit 87 is sent to a left-right directional dependency control circuit 85. When the instruction is in VLIW mode, the control unit 85 makes division output ineffective. When left-right directional dependency is found, a division instruction from the decoder 82 is sent to a microinstruction generator 98 which generates parallel microinstructions to be sent from a transmitting circuit 99 to the parallel execution pipelines 13 to 16 through a transmission line 100. Division bits are set in a microinstruction and the data dependency is eliminated.

公开(公告)号：JP2000330789A

公开(公告)日：2000-11-30

申请号：JP2000134667

申请日：2000-05-08

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  FEL BRUNO ,  DUCOUSSO LAURENT

IPC: G06F9/30 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To effectively transfer a protection value between execution units by providing a protection value transfer circuit which can transfer the protection value from master protection to an execution unit. SOLUTION: Each instruction has a protection indicator. A master protection register file is a protection register file 27 of a data unit 18 and a shadow protection register file is given by a control protection register file 101 of a control unit 12. When a data unit 18 executes a protection transmit instruction, a proper protection value is transferred to an address unit 19 or data memory interface control 50. The transferred protection value is held in an A-IDQ protection queue 113 or ARLQ protection queue 114. As for a storage instruction having a storage address added to SAQ 71 of interface control 50, the protection value is transferred from a circuit 112 to an SAQ protection queue 115.

公开(公告)号：JP2000286270A

公开(公告)日：2000-10-13

申请号：JP2000068526

申请日：2000-03-13

Applicant: ST MICROELECTRONICS SA

Inventor： GRIS YVON ,  TROILLARD GERMAINE

IPC: H01L29/417 ,  H01L21/225 ,  H01L21/265 ,  H01L21/331 ,  H01L29/73 ,  H01L29/732

Abstract: PROBLEM TO BE SOLVED: To reduce resistance of a base-emitter junction by a method, wherein a silicon nitride, and next a silicon oxide are deposited and etched, and these layers are anisotropically etched and cleaned, and a silicon oxide layer is re- etched. SOLUTION: A thermal oxide 16 is grown on the surface of a substrate 11 as the bottom part of a window W, and on the side face exposed of a polysilicon layer 13. Next, a base region 17 is formed by injection through the thin oxide 16. Next, a silicon nitride layer 18 is equiangularly deposited, next a spacer is formed, and therefore a silicon oxide layer 19 of, for example a thickness of about 150 nm is equiangularly deposited. Next, the oxide layer 19 is anisotropically etched, and the spacer is left behind, and thereafter the nitride layer 18 and the thermal oxide layer 16 are anisotropically etched. Next, cleaning is preferably performed at three stages, and the spacer formed by the layer 19 on a wall of the window W is partially re-etched. As a result, a flare-type profile can be obtained.

公开(公告)号：JP2000224200A

公开(公告)日：2000-08-11

申请号：JP2000020023

申请日：2000-01-28

Applicant: ST MICROELECTRONICS SA

Inventor： MONIOT PASCAL

IPC: H04L13/08 ,  H04L12/54 ,  H04L12/70 ,  H04Q11/04 ,  H04L12/28

Abstract: PROBLEM TO BE SOLVED: To control the speed of multiplex transmission, having different speed restrictions on the same communication channel by writing an index corresponding to transmission having a high priority order in a first queue and writing the index, corresponding to transmission having a lower priority order in a second queue. SOLUTION: The connection written in a queue 18a is processed by the priority order related to connection which is written in a queue 18b. A connection to which the high priority order has to be assigned (CBR connection and real-time VBR connection) is written in the queue 18a, and other connections (VBR connection which is not in real-time, ABR connection and UBR connection) are written in the queue 18b. The queue 18a includes multiple continuous indexes so that a ghost index is written, in order to avoid the situation in which the connection of the queue 18b is not processed in time. The method avoides concentration of the continuous indexes in the queue 18a and enables processing periodically in the queue 18b.

公开(公告)号：JP2000224138A

公开(公告)日：2000-08-11

申请号：JP2000017221

申请日：2000-01-26

Applicant: ST MICROELECTRONICS SA

Inventor： MAZZONI SIMONE ,  CAMBONIE JOEL

IPC: H04J11/00 ,  H04L27/26

Abstract: PROBLEM TO BE SOLVED: To specially reduce a transmission delay by permitting a last sample forming a symbol before a shift to be placed at the beginning of the symbol, after the shift to directly form a prefix. SOLUTION: A complex coefficient Ai.ejϕi is added to an IFFT circuit 12 through a complex multiplier 22 in the case that i belongs to [1, N]. The N coefficients eiKiτ are respectively added to the second input of the multiplier 22 in correspondence. The IFFT circuit outputs a first sample S1' of the symbol Dt' with a time t1 and a memory 24 stores the sample which is controlled in a writing mode. A multiplexer 16 is changed-over and selects the output of the circuit 12. The state of a circuit 10 is kept in a state without changes, until a time tτ. Thus, the samples from S1' to Sj' can be stored in the memory 24 and cyclic prefixes formed by S1' to Sj' are given to the output of the multiplexer 16.

公开(公告)号：JP2000115032A

公开(公告)日：2000-04-21

申请号：JP28134099

申请日：1999-10-01

Applicant: ST MICROELECTRONICS SA ,  TELIA AB

Inventor： MESTDAGH DENIS J G ,  ISAKSSON MIKAEL R ,  OEKVIST GOERAN S

IPC: H04B3/23 ,  H04J11/00 ,  H04L27/26

Abstract: PROBLEM TO BE SOLVED: To provide a digital subscriber line transmission system having an echo canceller simple in configuration and high in reliability. SOLUTION: This system has an inverse fast Fourier transformation (IFFT) circuit 14 which receives N digital output values as frequency range coefficients, a fast Fourier transformation(FFT) circuit 18 which receives a time area signal and outputs N digital frequency range coefficients as input values, a line interface 16 which couples the IFFT and FFT circuit with a subscriber line 10, and a circuit which inserts cyclic suffixes(CS) at ends of respective symbols while the symbols are part of the time area signal corresponding to the N output values and includes the echo canceler provided so as to subtract the respective output values mutiplied by respective constant magnifications (k) from the respective input values.

公开(公告)号：JP2000041077A

公开(公告)日：2000-02-08

申请号：JP16972099

申请日：1999-06-16

Applicant: ST MICROELECTRONICS SA

Inventor： MEYER JACQUES

IPC: H03L7/095 ,  H04L7/00 ,  H04L27/00 ,  H04L27/22 ,  H04L27/227

Abstract: PROBLEM TO BE SOLVED: To speedily and accurately detect a lock-in state with a simple process by calculating the module of a vector including as components two couples of values of a QPSK demodulator and determining lock-in conditions according to the number of modules different from a threshold. SOLUTION: A computation unit 20 calculates the module of the vector including as components of a couple of Is and Qs value corresponding to a binary value from a demodulator, i.e., the distance (r) between the point corresponding to Is and Qs and the original point of the arrangement, and a comparator 22 compares it with a threshold distance rth stored in a register 24. According to the comparison result, an adder 26 adds +A or -B from a multiplexer 28 and subtract rth to update the rth in the register 24. A respective process is performed as to the number of charges to automatically adjust the ratio of rth and (r) to A/A+B. An analyzing circuit 30 analyzes variation in rth and activates a lock-in signal LCK when a certain condition wherein rth fall within a range of specific noise-to-signal ratios is met.

公开(公告)号：JPH11354640A

公开(公告)日：1999-12-24

申请号：JP13525599

申请日：1999-05-17

Applicant: ST MICROELECTRONICS SA

Inventor： GAYET PHILIPPE ,  GRANGER ERIC

IPC: H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To control electrical resistance between a wiring and a via of an integrated circuit. SOLUTION: A first dielectric layer 10 and a second dielectric layer 11, which can be selectively etched to the first dielectric layer 10, are deposited on an n-level wiring layer. A hole 13 is formed by etching the first and second dielectric layers and is charged with metal, and via 14 is formed. A third dielectric layer 15 is deposited on the second dielectric layer 11 and the via. The third dielectric layer 15 and the second dielectric layer 11 are etched for forming trenches 18, 19, and etching is stopped on the first dielectric layer 10. The trenches 18, 19 are charged with metal and n-th level and (n+1)-th level wirings are electrically connected by the via 14. Even when there is an offset between via 14 and a wire 20, it is possible to know the height of a side surface part 20a which is in electrical contact therewith and to control the electrical resistance.

公开(公告)号：JPH11297637A

公开(公告)日：1999-10-29

申请号：JP6481399

申请日：1999-03-11

Applicant: ST MICROELECTRONICS SA ,  KONINKL PHILIPS ELECTRONICS NV

Inventor： GERRITSEN ERIC ,  BAYLAC BRUNO ,  BASSO MARIE-THERESE

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To form a titanium silicide layer having low resitivity by depositing a specific metal element on an interface between a titanium layer and a doped region before annealing a substrate whose doped region is covered with a titanium layer to form the titanium silicide layer. SOLUTION: A gate 5 is formed and then is doped with phosphorus atoms to reduce depletion thereof. Next, spacers 6, 7 are formed and then arsenic or boron is implanted to form source and drain regions 8, 9 and then indium atoms are implanted. Next, a titanium layer 10 is deposited and then TiN is selectively deposited. Then, titanium silicide contacts 11, 12, 13 having low resitivity (C54 phase) are formed by a rapid thermal annealing treatment. The not-reacted portions of the titanium layer 10 and TiN are selectively etched away.

公开(公告)号：JPH11243190A

公开(公告)日：1999-09-07

申请号：JP36275198

申请日：1998-12-21

Applicant: ST MICROELECTRONICS SA

Inventor： RAULT PIERRE ,  BERNIER ERIC

IPC: H01L29/74 ,  H01L27/06 ,  H01L27/08 ,  H01L29/747 ,  H03K17/00 ,  H03K17/0814 ,  H03K17/725

Abstract: PROBLEM TO BE SOLVED: To provide a normally-on bidirectional switch, which is lessened in power consumption in an off-state and in number of required elements by a method, wherein a switch in which two thyristors each related to positive half- wave and the negative half-wave of an alternating supply voltage are used is additionally provided. SOLUTION: A switch 3 is equipped with a first cathode-gate thyristor 39 which is connected in parallel between power supply terminals 32 and 33, and the anode of the thyristor 39 is connected to the first power supply terminal 33. Furthermore, the switch 3 is equipped with a second anode-gate thysristor 40, and the anode of the thyristor 40 is connected to the other power supply terminal 32. A gates Gc and Ga of the thyristors 39 and 40 is connected to the power supply terminal 33 through the same resistor R3 and the terminal 32 through a control switch 34. A protective diode 41 is interposed between the cathode of the thyristor 40 and the terminal 33. With this setup, a thyristor is not required to be used as an active power switch, and moreover the required high-voltage devices can be reduced in number.