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106 records (took 0.024 seconds)

    96.
    发明专利
    未知

    公开(公告)号：DE50004329D1

    公开(公告)日：2003-12-11

    申请号：DE50004329

    申请日：2000-03-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  BRAUN GEORG ,  HOENIGSCHMID HEINZ ,  MANYOKI ZOLTAN ,  ROEHR THOMAS

    IPC: G11C11/401 ,  G11C7/14 ,  G11C11/22

    Abstract: The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the reference cells from the read amplifiers via first switching elements, and by electrically connecting the part of the bit lines that is connected to the reference cells via second switching elements to a potential line carrying the reference information.

    97.
    发明专利
    未知

    公开(公告)号：DE10310779A1

    公开(公告)日：2003-11-20

    申请号：DE10310779

    申请日：2003-03-12

    Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

    Inventor： TAKASHIMA DAISABURO ,  SHIRATAKE SHINICHIRO ,  JOACHIM HANS-OLIVER ,  ROEHR THOMAS

    IPC: G11C8/08 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/105

    Abstract: A chained memory IC in which a dual voltage scheme is used for operating the wordlines is described. During standby mode, the wordlines are maintained at a first logic 1 voltage level. To prepare for a memory access, the non-selected wordlines are driven to a boosted voltage while the selected wordline is driven to ground. The first logic 1 voltage level is less than the boosted voltage. This reduces the stress on the gate oxide of the transistors, thus improving reliability of the memory IC.

    98.
    发明专利
    未知

    公开(公告)号：DE59903679D1

    公开(公告)日：2003-01-16

    申请号：DE59903679

    申请日：1999-09-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROEHR THOMAS ,  BOEHM THOMAS ,  HOENIGSCHMID HEINZ ,  BRAUN GEORG

    IPC: G11C11/409 ,  G11C7/12 ,  G11C7/22 ,  G11C11/22

    Abstract: The memory has writable memory cells. In addition, it has a bit line pair which connects the memory cells MC to a differential sense amplifier. A control unit is used for precharging the bit lines in a plurality of steps before one of the memory cells is conductively connected to one of the bit lines for a read access operation. For a write access operation, the control unit carries out no more than some of the bit line precharging steps provided for a read access operation before the sense amplifier transfers data to the bit line pair.

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