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公开(公告)号:CA2912469A1
公开(公告)日:2014-12-31
申请号:CA2912469
申请日:2014-06-27
Applicant: QUALCOMM INC
Inventor: THIRUMALAI VIJAYARAGHAVAN , ZHANG LI , CHEN YING
IPC: H04N19/51 , H04N19/597
Abstract: An example video coding device is configured to compare an inter-view predicted motion vector candidate (IPMVC) to a motion vector inheritance (MVI) candidate, where the IPMVC and the MVI candidate are each associated with a block of video data in a dependent depth view, and where the IPMVC is generated from a corresponding block of video data in a base depth view. The video coding device may be further configured to perform one of adding the IPMVC to a merge candidate list based on the IPMVC being different from the MVI candidate, or omitting the IPMVC from the merge candidate list based on the IPMVC being identical to the MVI candidate.
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公开(公告)号:CA2912451A1
公开(公告)日:2014-12-24
申请号:CA2912451
申请日:2014-06-20
Applicant: QUALCOMM INC
Inventor: ZHANG LI , CHEN YING , KARCZEWICZ MARTA
IPC: H04N19/597 , H04N19/61
Abstract: Techniques for advanced residual prediction (ARP) for coding video data may include inter-view ARP. Inter-view ARP may include identifying a disparity motion vector (DMV) for a current video block. The DMV is used for inter-view prediction of the current video block based on an inter-view reference video block. The techniques for inter-view ARP may also include identifying temporal reference video blocks in the current and reference views based on a temporal motion vector (TMV) of the inter-view reference video block, and determining a residual predictor block based on a difference between the temporal reference video blocks.
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公开(公告)号:PH12014501923B1
公开(公告)日:2014-11-24
申请号:PH12014501923
申请日:2014-08-27
Applicant: QUALCOMM INC
Inventor: CHEN YING , WANG YE-KUI , ZHANG LI
IPC: H04N7/12 , H04N11/02 , H04N19/51 , H04N19/52 , H04N19/597
Abstract: In one example, a device includes a video coder (e.g., a video encoder or a video decoder) configured to determine that a block of video data is to be coded in accordance with a three-dimensional extension of High Efficiency Video Coding (HEVC), and, based the determination that the block is to be coded in accordance with the three- dimensional extension of HEVC, disable temporal motion vector prediction for coding the block. The video coder may be further configured to, when the block comprises a bi-predicted block (B-block), determine that the B-block refers to a predetermined pair of pictures in a first reference picture list and a second reference picture list, and, based on the determination that the B-block refers to the predetermined pair, equally weight contributions from the pair of pictures when calculating a predictive block for the block.
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公开(公告)号:AU2013231961A1
公开(公告)日:2014-09-25
申请号:AU2013231961
申请日:2013-03-14
Applicant: QUALCOMM INC
Inventor: CHEN YING , WANG YE-KUI , ZHANG LI
IPC: H04N19/00 , H04N19/50 , H04N19/503
Abstract: In one example, a device includes a video coder configured to code a picture order count (POC) value for a first picture of video data, code a second-dimension picture identifier for the first picture, and code, in accordance with a base video coding specification or an extension to the base video coding specification, a second picture based at least in part on the POC value and the second-dimension picture identifier of the first picture. The video coder may comprise a video encoder or a video decoder. The second-dimension picture identifier may comprise, for example, a view identifier, a view order index, a layer identifier, or other such identifier. The video coder may code the POC value and the second-dimension picture identifier duing coding of a motion vector for a block of the second picture, e.g., during advanced motion vector prediction or merge mode coding.
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公开(公告)号:CA2543036C
公开(公告)日:2011-06-28
申请号:CA2543036
申请日:2004-10-18
Applicant: QUALCOMM INC
Abstract: An integrated circuit that performs data demodulation on partially despread symbols includes a despreading unit (620), a channel compensation unit (640), and a symbol combiner (650). The despreading unit (620) despreads input samples and provides despread symbols for a first code channel with a first spreading factor. The channel compensation unit (640) multiplies the despread symbols with channel estimates and provides demodulated symbols. The symbol combiner (650) combines groups of demodulated symbols to obtain recovered data symbols for a second code channel with a second spreading factor that is an integer multiple of the first spreading factor. The channel compensation and symbol combining are dependent on whether or not transmit diversity is used. For a TDM design, despread symbols for multiple first code channels are processed in a TDM manner, one channel at a time, to obtain recovered data symbols for multiple second code channels. The channel compensation unit and symbol combiner can be operated in a pipelined manner.
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公开(公告)号:DE69925720T2
公开(公告)日:2006-03-16
申请号:DE69925720
申请日:1999-03-04
Applicant: QUALCOMM INC
Inventor: SIH C , ZOU QUIZHEN , JHA K , KANG INYUP , LIN JIAN , MOTIWALA QUAEED , JOHN DEEPU , ZHANG LI , ZHANG HAITAO , LEE WAY-SHING , SAKAMAKI E , KANTAK A
Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).
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公开(公告)号:AT297567T
公开(公告)日:2005-06-15
申请号:AT99911150
申请日:1999-03-04
Applicant: QUALCOMM INC
Inventor: SIH GILBERT C , ZOU QUIZHEN , JHA SANJAY K , KANG INYUP , LIN JIAN , MOTIWALA QUAEED , JOHN DEEPU , ZHANG LI , ZHANG HAITAO , LEE WAY-SHING , SAKAMAKI CHARLES E , KANTAK PRASHANT A
Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).
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公开(公告)号:CA2543036A1
公开(公告)日:2005-04-28
申请号:CA2543036
申请日:2004-10-18
Applicant: QUALCOMM INC
Abstract: An apparatus for performing data demodulation, comprising means for despreading to despread input samples and provide despread symbols for plurality of first code channels with a first spreading factor; means for multiplying to multiply the despread symbols for each of the plurality of first code channels with channel estimates and provide demodulated symbols for the first code channel; and means for combining to combine groups of demodulated symbols for each of the plurality of first code channels to obtain recovered data symbols for a set of second code channels with a second spreading factor and corresponding to the first code channel, the second spreading factor being an integer multiple of the first spreading factor and a corresponding method.
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公开(公告)号:ES3009439T3
公开(公告)日:2025-03-26
申请号:ES18198746
申请日:2015-01-09
Applicant: QUALCOMM INC
Inventor: LI XIANG , SOLE ROJALS JOEL , KARCZEWICZ MARTA , LIU HONGBIN , ZHANG LI , CHEN JIANLE
IPC: H04N19/56 , H04N19/44 , H04N19/51 , H04N19/523 , H04N19/53 , H04N19/533
Abstract: Un método de codificación de datos de vídeo comprende determinar un valor de diferencia de vector de movimiento para un bloque actual de datos de vídeo y, en respuesta a que el valor de diferencia de vector de movimiento sea igual a cero, determinar que un vector de movimiento para el bloque actual tiene una precisión de vector de movimiento de subpíxeles. (Traducción automática con Google Translate, sin valor legal)
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公开(公告)号:PL3639519T3
公开(公告)日:2023-11-27
申请号:PL18735138
申请日:2018-06-11
Applicant: QUALCOMM INC
Inventor: CHEN YI-WEN , CHIEN WEI-JUNG , SUN YU-CHEN , ZHANG LI , LEE SUNGWON , LI XIANG , CHUANG HSIAO-CHIANG , CHEN JIANLE , SEREGIN VADIM , KARCZEWICZ MARTA
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