Abstract:
Plural pins (3) are arranged on a printed circuit board (1) to form a generally square shape and are electrically connected to terminals of a QFP-IC (2). In the pins (3), a pin disposed at a corner portion of the generally square shape is used as a GND terminal (3a), and a pin adjoining the GND terminal is used as a source terminal (3b). A conductive region (5a) is provided to extend radially from the corner portion, and is electrically connected to the ground terminal (3a). Further, another conductive region (5b) is provided in the generally square shape and is electrically connected to the radial conductive region (5a).
Abstract:
An etched tri-metal-layer air bridge circuit board specially designed for fine-pitch applications, comprising: an electrically insulative substrate surface (10), a plurality of tri-metal-layer bond pads (12) arranged in a generally straight row on the substrate surface (10) wherein the row defines a width direction therealong, and a circuit trace (20) arranged on the substrate surface (10), wherein the circuit trace (20) runs between two adjacent ones (22) of the plurality of tri-metal-layer bond pads (12). Each bond pad (12) comprises: (1) a bottom layer (14) attached to the substrate surface (10), the bottom layer (14) being made of a first metal and having an overall width W1 as measured along the width direction; (2) a top layer (18) disposed above and generally concentric with the bottom layer (14), the top layer (18) being made of the first metal and having an overall width W2 as measured along the width direction; and (3) a middle layer (16) made of a second metal connecting the bottom layer (14) and the top layer (18). The bond pads (12) are specially shaped such that W2 > W1 for at least the two adjacent bond pads (12), thus enabling the circuit trace (20) to be spaced closely to the bottom layers (14) of the two adjacent bond pads (12), while allowing the top layers (18) of the pads (12) to be made much larger so as to avoid delamination thereof from their associated middle layers (16).
Abstract:
A multilayer printed circuit memory board is designed and constructed so that the top and bottom layers contain repetitive integrated circuit (IC) chip component hole/pad and interconnection line patterns which are mirror images of one another. The board uses surface mounted techniques in which the integrated chip components of the memory array are mounted and soldered to both sides of the board thereby doubling the density or capacity of the memory board. The integrated circuit memory chips, mounted on the top and bottom of the board, are aligned with each other for sharing common holes or vias in which logically equivalent input signal connections are exchanged in a manner for reducing the number of holes and length of connective wiring.
Abstract:
A multilayer printed circuit memory board is designed and constructed so that the top and bottom layers contain repetitive integrated circuit (IC) chip component hole/pad and interconnection line patterns which are mirror images of one another. The board uses surface mounted techniques in which the integrated chip components of the memory array are mounted and soldered to both sides of the board thereby doubling the density or capacity of the memory board. The integrated circuit memory chips, mounted on the top and bottom of the board, are aligned with each other for sharing common holes or vias in which logically equivalent input signal connections are exchanged in a manner for reducing the number of holes and length of connective wiring.
Abstract:
Un module de circuit, ou un autre dispositif (10) est monté sur une carte de circuit imprimé, ou un autre substrat (14), une structure (30) de fil métallique de résistance sinueux électroconducteur étant intercalée pour définir un espace rempli d'adhésif. Lorsque l'adhésif a durci, le module est maintenu en place. Lorsqu'on désire enlever le module, on fait passer un courant à travers la structure de fil métallique sinueux afin de ramollir l'adhésif en vue de permettre la dépose du module sans endommager ce dernier ou la carte de circuit imprimé.
Abstract:
A printed circuit board includes a layered substrate having a plurality of layers having an electrical connector footprint configured to receive an electrical connector. The printed circuit board includes pair anti-pads passing through the layered substrate around pairs of signal vias. The printed circuit board includes ground vias passing through the layered substrate. The ground vias are configured to receive ground pins of the electrical connector. The ground vias are located outside of the pair anti-pads. The printed circuit board includes SI vias passing through the layered substrate. The SI vias form an SI fence surrounding the corresponding pair anti-pad.
Abstract:
Provided is a printed wiring board including a first heat dissipation pattern placed in one surface layer on which a semiconductor package is to be mounted, a second heat dissipation pattern placed in the other surface layer, and an inner layer conductor pattern placed in an inner layer, in which through holes are formed in the printed wiring board; the first heat dissipation pattern has a joint portion which is placed in an opposed region opposed to a heat sink of the semiconductor package and which is joined to the heat sink with solder; at least one of the through holes is placed in the opposed region; and the second heat dissipation pattern is formed in a pattern in which an end portion of a conductor film in the one of the through holes on the other surface layer side is separated.
Abstract:
A printed circuit board includes a board body having a routing-limited area. The routing-limited area is provided with at least one solder pad that is adapted for supporting a metal support thereon. Preferably, the printed circuit board further includes a protrusion block disposed on the solder pad, and having a height greater than that of a signal trace that passes the routing-limited area.