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    Integrated semiconductor device and method of manufacturing thereof
    101.
    发明公开
    Integrated semiconductor device and method of manufacturing thereof 审中-公开
    Integriertes Halbleiterbauelement和dessen Herstellungsverfahren

    公开(公告)号：EP1441393A2

    公开(公告)日：2004-07-28

    申请号：EP03016445.3

    申请日：2003-07-21

    Applicant: Renesas Technology Corp.

    Inventor： Nitta, Tetsuya, c/o Renesas Technology Corp. ,  Terashima, Tomohide, c/o Mitsubishi Denki Kab. Ka.

    IPC: H01L27/12 ,  H01L21/84

    CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device (50) includes a plurality of semiconductor elements (50a, 50b, 50c) formed in a semiconductor layer and each having a source (6) of an n type semiconductor, a drain (3) of the n type semiconductor and a back gate (5) of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.

    Abstract translation: 包含具有各自所需导通电阻和击穿电压的半导体元件的集成半导体器件实现了作为整体半导体元件的整体的适当特性。 集成半导体器件（50）包括形成在半导体层中并且各自具有n型半导体源（6），n型半导体的漏极（3）和n型半导体的漏极（3）的多个半导体元件（50a，50b，50c） 在源极和漏极之间的ap型半导体的背栅（5）。 至少一个半导体元件的漏极的预定部分和另一半导体元件的漏极的预定部分具有彼此不同的杂质浓度。

    Semiconductor integrated circuit device and wireless communication system
    102.
    发明公开
    Semiconductor integrated circuit device and wireless communication system 有权
    Integrierte Halbleiterschaltung和Funk-Kommunikationssystem

    公开(公告)号：EP1418669A2

    公开(公告)日：2004-05-12

    申请号：EP03023256.5

    申请日：2003-10-14

    Applicant: Renesas Technology Corp.

    Inventor： Irie, Kiyoshi, Renesas Technology Corp. ,  Hori, Kazuaki, Renesas Technology Corp. ,  Hikasa, Kazuhiko, Renesas Technology Corp.

    IPC: H03G3/30

    CPC classification number: H03G1/0088 ,  H03F3/45098 ,  H03F2200/294 ,  H03F2203/45496 ,  H03F2203/45504 ,  H03F2203/45722 ,  H03G1/0023 ,  H04B1/707 ,  H04B2201/70706

    Abstract: The dynamic range is changed by switching a current applied to an amplifying circuit to obtain the minimum ICP required to keep linearity with the number of multiplexes even when the number of multiplexes of data is changed by switching the operation current of the amplifying circuits of the transmission system and also supplying the information about number of multiplexes of data to be transmitted to the amplifying circuits of the transmission system from the baseband circuit. Thereby, the signal can be transmitted without distortion even when the number of multiplexes increases and the current of the amplifying circuit may be reduced when the number of multiplexes is small in order to reduce the current consumption in the communication semiconductor integrated circuit device which can form a wireless communication system of the code division multiplex system such as W-CDMA system.

    Abstract translation: 通过切换施加到放大电路的电流来改变动态范围，以便即使当通过切换传输的放大电路的操作电流来改变数据的多路复用数量时，获得与多路复用数保持线性关系所需的最小ICP 并且还从基带电路向发送系统的放大电路提供关于要发送的数据的复用数量的信息。 从而，即使多路复用数量增加，信号也可以无失真地发送，并且为了减少可形成的通信半导体集成电路装置的电流消耗，多路复用数量少时，放大电路的电流可能减小 诸如W-CDMA系统的码分多路复用系统的无线通信系统。

    high frequency power amplifier and wireless communication system
    103.
    发明公开
    high frequency power amplifier and wireless communication system 有权
    Hochfrequenzleistungsverstärkerund Funk-Kommunikationssystem

    公开(公告)号：EP1411632A2

    公开(公告)日：2004-04-21

    申请号：EP03023106.2

    申请日：2003-10-10

    Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co.,Ltd. ,  Hitachi Hybrid network Co., Ltd.

    Inventor： Takahashi, Kyoichi, Hitachi ULSI Systems Co. Ltd. ,  Matsudaira, Nobuhiro ,  Akamine, Hitoshi

    IPC: H03G3/30

    CPC classification number: H03G3/3047 ,  H03F2200/504

    Abstract: The present invention provides a high frequency amplifier suitable for use in a wireless communication system which performs detection of an output level necessary for feedback control by a current detection system, wherein control sensitivity in an area low in transmit request level is lowered so that an output level can be controlled over the whole control range with satisfactory accuracy. There is provided a high frequency power amplification electric part constituting a wireless communication system, which performs detection of an output level necessary for feedback control of output power by a current detection system, compares the output level detected signal and an output level designation signal and generates a bias voltage for a high frequency power amplifier according to the difference therebetween to thereby control gain, wherein an nth root converter or a logarithm converter is provided between a current detector and a current-voltage converter.

    Abstract translation: 检测器响应功率放大器的输入信号检测功率放大器的电流。 将转换的电压与输出电平指定信号进行比较，并输出与该差值对应的信号。 检测器的输出电流被转换为不具有局部最大值且以向上凸形单调增加的函数所表示的电流。 无线通信系统还包括独立的索赔。

    Semiconductor integrated circuit device
    107.
    发明公开
    Semiconductor integrated circuit device 有权
    Integrierte Halbleiterschaltung

    公开(公告)号：EP2065893A1

    公开(公告)日：2009-06-03

    申请号：EP08253714.3

    申请日：2008-11-13

    Applicant: Renesas Technology Corp.

    Inventor： Kajiyama, Shinya ,  Shinagawa, Yutaka ,  Mizuno, Makoto ,  Kasai, Hideo ,  Watanabe, Takao ,  Takemura, Riichiro ,  Sekiguchi, Tomonori

    IPC: G11C7/10

    CPC classification number: G11C7/1039 ,  G11C7/1075 ,  G11C16/26

    Abstract: The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.

    Abstract translation: 半导体集成电路装置包括：第一锁存器，其可以保持X解码器的输出信号，并且在X解码器之后的后级将信号传送到字驱动器; 第二锁存器，其可以保持Y解码器的输出信号，并且在Y解码器之后的后级中将信号传送到列多路复用器; 以及第三锁存器，其可以保持读出放大器的输出信号，并且在读出放大器之后的后级中将该信号传送到输出缓冲器。 该结构使得可以管理一系列用于读取存储在非易失性半导体存储器中的数据的处理，并且即使在来自CPU的访问请求冲突的情况下也能够进行低延迟访问。

    Electronic device and RF module
    109.
    发明公开
    Electronic device and RF module 审中-公开
    电子设备和射频模块

    公开(公告)号：EP1956615A2

    公开(公告)日：2008-08-13

    申请号：EP07254736.7

    申请日：2007-12-07

    Applicant: Renesas Technology Corp.

    Inventor： Takahashi, Wataru ,  Tsuchida, Shigeru ,  Okabe, Hiroshi

    IPC: H01F17/00 ,  H05K1/02 ,  H05K1/16 ,  H04B1/38 ,  H01L23/48 ,  H01L23/52 ,  H01L23/64

    CPC classification number: H05K1/165 ,  H01F17/0006 ,  H01L2924/0002 ,  H03H7/0115 ,  H03H7/1758 ,  H03H7/1766 ,  H03H7/383 ,  H03H7/465 ,  H03H2001/0085 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/16 ,  H05K3/429 ,  H05K2201/09636 ,  H05K2201/09672 ,  H01L2924/00

    Abstract: A parallel resonant circuit is realized by stacking first to fourth wiring patterns each having at least an inductance element. One of the adjacent first and second wiring patterns is set to a signal input node and the other thereof is set to a signal output node. Then, the signal input node is connected to the signal output node via inductance elements of the first wiring pattern, third wiring pattern, fourth wiring pattern and second wiring pattern in order. By adjacently forming wiring layers of the signal input and output nodes, a capacitance value between the input and output nodes is increased compared to that when they are separated. Also, by increasing the line width of the first and second wiring patterns, the capacitance value can be further increased. Therefore, it is possible to achieve a large capacitance value in a small area and downsizing of the electronic device.

    Abstract translation: 通过层叠至少具有电感元件的第一至第四布线图案来实现并联谐振电路。 相邻的第一布线图案和第二布线图案中的一个被设置为信号输入节点，另一个被设置为信号输出节点。 然后，信号输入节点依次经由第一布线图案，第三布线图案，第四布线图案和第二布线图案的电感元件连接到信号输出节点。 通过相邻地形成信号输入和输出节点的布线层，与分离时相比，输入和输出节点之间的电容值增加。 而且，通过增加第一布线图案和第二布线图案的线宽，可以进一步增加电容值。 因此，可以实现小面积的大电容值和电子设备的小型化。

    SEMICONDUCTOR DEVICE
    110.
    发明公开
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：EP1953824A1

    公开(公告)日：2008-08-06

    申请号：EP06832623.0

    申请日：2006-11-14

    Applicant: Renesas Technology Corp.

    Inventor： MORIKAWA, Takahiro ,  TERAO, Motoyasu ,  TAKAURA, Norikatsu ,  KUROTSUCHI, Kenzo

    IPC: H01L27/105 ,  H01L45/00

    CPC classification number: H01L27/2463 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

    Abstract: On the same semiconductor substrate 1, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layer 22 storing a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layer 22 is made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom% or larger to 40 atom% or smaller, Ge of 5 atom% or larger to 35 atom% or smaller, Sb of 5 atom% or larger to 25 atom% or smaller, and Te of 40 atom% or larger to 65 atom% or smaller.

    Abstract translation: 在同一半导体基板1上形成有多个存储元件R，该存储元件阵列R具有存储高电阻值的高电阻状态和低电阻值的低电阻状态的硫属化物材料存储层22 通过原子排列的变化的值被排列成矩阵形成在存储单元区域中，并且半导体集成电路形成在逻辑电路区域lgc中。 该硫族化物材料存储层22由含有10.5原子％以上且40原子％以下的Ga或In中的至少一者，5原子％以上至35原子％以下的Ge，硫化锑材料 5原子％以上且25原子％以下，Te为40原子％以上且65原子％以下。

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