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公开(公告)号：KR1020080060881A
公开(公告)日：2008-07-02
申请号：KR1020060135495
申请日：2006-12-27
Applicant: 삼성전자주식회사
CPC classification number: G01R31/2896 , G01R1/0433 , G01R31/2867 , H01L22/30
Abstract: A method for testing a semiconductor package is provided to test the semiconductor package stably irrespective of the sort of the semiconductor package by controlling the drop height of a handler using a contact signal which is applied to a contact terminal. A method for testing a semiconductor package includes the steps of: determining the sort of the semiconductor package(S310); transmitting a contact signal to all contact terminals(S320); dropping a handler with a predetermined first stroke based on the sort of the semiconductor package(S330); determining whether a predetermined number of contact terminals are in contact with the semiconductor package through the contact signal(S340); dropping the handler with a predetermined second stroke irrespective of the sort of the semiconductor package if the contact terminals are in contact with the semiconductor package(S350); and transmitting a detection signal to the contact terminals if the drop of the handler is completed(S360).
Abstract translation: 提供了一种用于测试半导体封装的方法，通过使用施加到接触端子的接触信号来控制处理器的下降高度来稳定地测试半导体封装的类型，而不管半导体封装的种类。 一种用于测试半导体封装的方法包括以下步骤：确定半导体封装的种类（S310）; 向所有接触端子发送接触信号（S320）; 基于半导体封装的种类，以预定的第一行程丢弃处理程序（S330）; 通过接触信号确定预定数量的接触端子是否与半导体封装接触（S340）; 如果接触端子与半导体封装接触，则不管半导体封装的种类如何，以预定的第二笔划落下处理器（S350）。 以及如果处理器的下降完成，则将检测信号发送到接触端子（S360）。
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公开(公告)号：KR1020080021867A
公开(公告)日：2008-03-10
申请号：KR1020060084969
申请日：2006-09-05
Applicant: 삼성전자주식회사
IPC: H01L21/8242 , H01L21/768
Abstract: A method for fabricating a semiconductor device is provided to prevent happening of etching unbalance by forming a floating gate with only one polysilicon layer. A pattern having an aperture(114) is formed on a substrate(100) to expose a surface of the substrate. The substrate is heated at a temperature of 570 to 700 deg.C. A polysilicon layer(130) is formed to cover the pattern in such a way that the aperture of the pattern is buried at a deposition rate of 60 Angstrom per minute. The substrate is subjected to annealing by heating the substrate at a temperature of 780 to 900 deg.C for 10 to 50 minutes. In the annealing step, the substrate is heated at a rate of 1 to 10 deg.C per minute.
Abstract translation: 提供一种用于制造半导体器件的方法，以通过仅形成一个多晶硅层的浮栅来防止蚀刻不平衡的发生。 具有孔径（114）的图案形成在基板（100）上以暴露基板的表面。 将基板在570〜700℃的温度下加热。 形成多晶硅层（130）以覆盖图案，使得图案的孔径以每分钟60埃的沉积速率被掩埋。 通过在780〜900℃的温度下加热基板10〜50分钟对基板进行退火。 在退火步骤中，以1〜10℃/分钟的速度加热基板。
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公开(公告)号：KR1020080002030A
公开(公告)日：2008-01-04
申请号：KR1020060060569
申请日：2006-06-30
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/42324 , H01L21/28273 , H01L29/66833
Abstract: A method for forming a gate structure of a non-volatile memory device is provided to improve a leakage current characteristic and a threshold voltage scattering of the non-volatile memory device by forming an interlayer dielectric made of a dual layer composed of a silicon oxide layer and a silicon oxynitride layer. A tunnel dielectric layer pattern(110a) and a floating gate(120a) are sequentially formed on a semiconductor substrate(100). An interlayer dielectric pattern(130a) is formed on the floating gate, and has a dual layer structure of a silicon oxide layer and a silicon oxynitride layer. A control gate(140a) is formed on the interlayer dielectric pattern. The silicon oxynitride layer is formed on the silicon oxide layer by an LPCVD(Low Pressure Chemical Vapor Deposition) process.
Abstract translation: 提供了一种用于形成非易失性存储器件的栅极结构的方法，用于通过形成由二氧化硅层构成的双层形成的层间电介质来改善非易失性存储器件的漏电流特性和阈值电压散射 和氮氧化硅层。 隧道介质层图案（110a）和浮动栅极（120a）依次形成在半导体衬底（100）上。 在浮置栅极上形成层间电介质图案（130a），并且具有氧化硅层和氮氧化硅层的双层结构。 在层间电介质图案上形成控制栅极（140a）。 通过LPCVD（低压化学气相沉积）工艺在氧化硅层上形成氧氮化硅层。
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公开(公告)号：KR100757335B1
公开(公告)日：2007-09-11
申请号：KR1020060101158
申请日：2006-10-18
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L29/7881 , H01L29/66825 , H01L21/28273 , H01L27/11521
Abstract: A non-volatile memory device and a method for fabricating the same are provided to ensure a sufficient interval between an active region and a control gate electrode and reduce an electrical disturbance therebetween. A tunnel insulating layer(120) is formed on an active region(100b) of a substrate. Field insulating patterns(126) are formed on a surface of the substrate to define the active region, and upper recesses(128) are formed on upper surfaces of the field insulating patterns. A stack structure consisting of a floating gate electrode, a blocking film and a control gate electrode is formed on the tunnel insulating layer. Impurity diffusion regions are formed around the active region.
Abstract translation: 提供了一种非易失性存储器件及其制造方法，以确保有源区域和控制栅电极之间的足够的间隔并减小它们之间的电气干扰。 在衬底的有源区（100b）上形成隧道绝缘层（120）。 场绝缘图案（126）形成在衬底的表面上以限定有源区，并且上凹部（128）形成在场绝缘图案的上表面上。 在隧道绝缘层上形成由浮栅电极，阻挡膜和控制栅电极构成的堆叠结构。 在活性区周围形成杂质扩散区。
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Patent Agency Ranking
公开(公告)号：KR100641060B1
公开(公告)日：2006-11-01
申请号：KR1020050066674
申请日：2005-07-22
Applicant: 삼성전자주식회사
IPC: H01L21/336 , B82Y40/00
Abstract: A method of manufacturing a gate structure and a method of manufacturing a semiconductor device by using the same are provided to improve the character of the gate structure through a surface process fabrication. A gate oxidation layer(105) is fabricated on a substrate(100). The gate oxidation layer is processed by ozone water that includes ozone and deionized water. A silicon wafer or a silicon on insulator(SIO) is used as the substrate. The gate oxidation layer is formed by a thermal oxidation process or a chemical vapor deposit process. A gate conductive layer is formed by using a poly-silicon or a poly-SiGe on the gate oxidation layer which is processed by the ozone water. A mask layer is formed on the gate conductive layer. A mask pattern, a gate conductive pattern, and a gate oxidation layer pattern are formed by patterning the mask layer, the gate conductive layer, and the gate oxidation layer respectively. The gate oxidation layer is processed for 60 to 600 seconds.
Abstract translation: 提供了一种制造栅极结构的方法和使用该方法制造半导体器件的方法，以通过表面工艺制造来改善栅极结构的特性。 在衬底（100）上制造栅极氧化层（105）。 门氧化层由包括臭氧和去离子水的臭氧水处理。 使用硅晶片或绝缘体上硅（SIO）作为衬底。 栅极氧化层通过热氧化工艺或化学气相沉积工艺形成。 栅极导电层通过在由臭氧水处理的栅极氧化层上使用多晶硅或多晶硅锗来形成。 掩模层形成在栅极导电层上。 掩模图案，栅极导电图案和栅极氧化层图案分别通过图案化掩模层，栅极导电层和栅极氧化层而形成。 栅极氧化层处理60至600秒。
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公开(公告)号：KR100640626B1
公开(公告)日：2006-10-31
申请号：KR1020050000811
申请日：2005-01-05
Applicant: 삼성전자주식회사
IPC: H01L21/66
CPC classification number: G01R1/0466 , G01R1/0483 , G01R1/06722
Abstract: 고주파 대역은 물론 저주파 대역까지 측정할 수 있고, 수명이 긴 포고 핀 및 이를 포함하는 테스트 소켓에 대해 개시한다. 그 포고 핀 및 테스트 소켓은 반도체 패키지와 전기적으로 접촉하기 위하여 도전성 금속으로 이루어진 금속 플런저 및 금속 플런저와 연결되어 테스트 보드에 전기적으로 접촉하기 위하여 도전성 고무로 이루어진 고무접촉핀을 포함한다.
포고 핀, 테스트 소켓, 금속 플런저, 고무접촉핀-
公开(公告)号：KR1020060102879A
公开(公告)日：2006-09-28
申请号：KR1020050024934
申请日：2005-03-25
Applicant: 삼성전자주식회사
IPC: H01L21/8247
Abstract: 누설전류를 방지하며, 커패시턴스가 향상되는 불휘발성 메모리 셀의 제조방법에서, 기판의 상에 다결정 구조를 갖는 하부 폴리막과 비결정 구조를 갖는 상부 폴리막으로 이루어진 컨트롤 게이트층을 형성한다. 이어서, 상기 컨트롤 게이트층에 하부 산화막/ 금속 산화막/상부 산화막이 적층된 구조를 갖는 유전막을 형성한다. 이어서, 상기 유전막 상에 플로팅 게이트층을 형성함으로서 불휘발성 메모리 셀을 완성한다. 상기 불휘발성 메모리 셀은 커패시턴스가 현저하게 향상되고, 커플링 계수감소를 방지할 수 있다.
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