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公开(公告)号：KR1020090065272A
公开(公告)日：2009-06-22
申请号：KR1020070132758
申请日：2007-12-17
Applicant: 한국전자통신연구원
CPC classification number: G01N27/4146 , G01N27/4145 , Y10S977/71 , Y10S977/742 , Y10S977/963 , G01N33/48 , G01N23/00
Abstract: A biosensor is provided to lower operation current in sensing part of biomass lowering contact resistance between silicon nanowire and metal electrode. A biosensor comprises a silicon plate(200), source area(210), drain area(220), insulating layer(230) and silicon nano wire(240). The source area and drain area is arranged on the silicon plate. The insulating layer is arranged between source area and drain area. The silicon nano wire comprises defect area(241) and is arranged on the source area and drain area. A method for manufacturing the biosensor comprises: a step of preparing the silicon plate; a step of forming source area and drain area on the silicon plate; a step of arranging the silicon nano wire on the source area and drain area; and a step of irradiating electronic beam in one area of the silicon nano wire to form the defect area.
Abstract translation: 提供生物传感器来降低操作电流，以感测部分生物质降低硅纳米线与金属电极之间的接触电阻。 生物传感器包括硅板（200），源区（210），漏区（220），绝缘层（230）和硅纳米线（240）。 源极区域和漏极区域布置在硅板上。 绝缘层布置在源区和漏区之间。 硅纳米线包括缺陷区（241），并且布置在源区和漏区上。 制造所述生物传感器的方法包括：制备所述硅板的步骤; 在硅板上形成源区和漏区的步骤; 将硅纳米线布置在源极区域和漏极区域上的步骤; 以及在硅纳米线的一个区域中照射电子束以形成缺陷区域的步骤。
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公开(公告)号：KR1020090062373A
公开(公告)日：2009-06-17
申请号：KR1020070129581
申请日：2007-12-13
Applicant: 한국전자통신연구원
IPC: H01L21/336 , H01L29/78
CPC classification number: G01N27/4145 , H01L29/66818 , H01L29/7853
Abstract: A high sensitive sensor and a manufacturing method thereof are provided to obtain a high signal by controlling depletion and accumulation of a channel by combining a target material and a sensing material in both sides. An SOI(Silicon On Insulator) substrate is formed in an upper part of a semiconductor substrate. A mask pattern is formed by performing a lithography process in the upper part of the SOI substrate. The structure of a pin shape is formed by etching a silicon layer in the upper part of the SOI substrate. The sensor structure with a pin shaped structure is formed on the semiconductor substrate. A metal electrode is deposited by implanting the ion for electrical ohmic contact to the sensor structure. A sensing material combined in a target material is fixed in both sidewalls of the pin shaped structure. The path for penetrating the target material through the pin-shaped structure is formed on the sensor structure.
Abstract translation: 提供了一种高灵敏度传感器及其制造方法，以通过在两侧组合目标材料和感测材料来控制通道的耗尽和累积来获得高信号。 在半导体衬底的上部形成SOI（绝缘体上硅）衬底。 通过在SOI衬底的上部进行光刻工艺来形成掩模图案。 针状结构通过在SOI衬底的上部蚀刻硅层而形成。 具有针状结构的传感器结构形成在半导体衬底上。 通过将用于电欧姆接触的离子注入传感器结构来沉积金属电极。 组合在目标材料中的感测材料固定在销形结构的两个侧壁中。 在传感器结构上形成穿过针状结构穿透目标材料的路径。
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公开(公告)号：KR1020090058883A
公开(公告)日：2009-06-10
申请号：KR1020070125679
申请日：2007-12-05
Applicant: 한국전자통신연구원
CPC classification number: H01L29/0665 , B82Y10/00 , B82Y15/00 , H01L29/0673 , H01L29/78696
Abstract: A semiconductor nano wire sensor and a manufacturing method thereof are provided to implement a silicon nano wire channel of a line width with several nano meters by using a photolithographic process. A first conductive single crystal silicon line pattern is formed in the uppermost layer of an SOI(Silicon On Insulator) substrate. A second conductive channel(216b) is formed in both ends of the line width direction of the first conductive single crystal silicon line pattern. The second conductive pad is formed in both sides of the longitudinal direction of the first conductive single crystal silicon line pattern. A first electrode(242) for applying a reverse bias voltage is formed in an undoped region of the first conductive single crystal silicon line pattern. A second electrode(232) for applying the bias voltage to both sides of the second conductive channel is formed on the second conductive pad.
Abstract translation: 提供半导体纳米线传感器及其制造方法，通过使用光刻工艺来实现具有数纳米的线宽的硅纳米线通道。 在SOI（绝缘体上硅）衬底的最上层形成第一导电单晶硅线图形。 第二导电沟道（216b）形成在第一导电单晶硅线图案的线宽方向的两端。 第二导电焊盘形成在第一导电单晶硅线图案的纵向方向的两侧。 在第一导电单晶硅线图案的未掺杂区域中形成用于施加反向偏置电压的第一电极（242）。 在第二导电焊盘上形成用于将偏置电压施加到第二导电沟道两侧的第二电极（232）。
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公开(公告)号：KR1020090035209A
公开(公告)日：2009-04-09
申请号：KR1020070100350
申请日：2007-10-05
Applicant: 한국전자통신연구원
CPC classification number: H01J49/4205 , B81B7/0025 , B81B2201/0214 , B81B2201/0271 , B82Y10/00 , B82Y40/00 , G01N2291/0257 , H01J49/0018 , H01L29/0673 , H01L29/7613 , H01L29/775 , H03H2009/02314
Abstract: A three dimensional nano device including nano structures is provided to complement electrical devices and optical devices to each other by improving electrical characteristics of nano device presented in a two-dimensional plane structure. A three dimensional nano device including nano structures comprises: at least one nano structure having a vibration unit(111) formed above a substrate and a support unit(112) supporting the both ends of the vibration unit; a support stand(120) formed on the substrate to support the support unit of the nano structures; a controller, formed in an upper part or lower part of the substrate or both sides of the upper part and lower part, for controlling the nano structures; a sensing unit(150) formed on the vibration unit to sense materials which are flowed in from the outside; and an external vibration unit formed in the lower part of the substrate.
Abstract translation: 提供包括纳米结构的三维纳米器件，以通过改善呈现在二维平面结构中的纳米器件的电特性来彼此补充电子器件和光学器件。 包括纳米结构的三维纳米器件包括：至少一个纳米结构，其具有形成在衬底上方的振动单元（111）和支撑所述振动单元两端的支撑单元（112） 形成在所述基板上以支撑所述纳米结构的支撑单元的支撑台（120） 形成在基板的上部或下部或上部和下部的两侧的控制器，用于控制纳米结构; 感测单元（150），其形成在所述振动单元上以感测从外部流入的材料; 以及形成在基板的下部的外部振动单元。
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公开(公告)号：KR100883350B1
公开(公告)日：2009-02-11
申请号：KR1020070096342
申请日：2007-09-21
Applicant: 한국전자통신연구원
IPC: H01L29/47 , H01L21/336 , H01L29/78
Abstract: 본 발명은 소스 및 드레인 전극을 촉매로 하여 채널영역을 결정화시킬 수 있는 쇼트키 장벽 박막 트랜지스터(Schottky Barrier Thin Film Transistor) 제조방법에 관한 것으로, 이를 위한 본 발명의 쇼트키 장벽 박막 트랜지스터의 제조방법은 기판 상부에 비정질실리콘 활성층을 형성하는 단계; 상기 비정질실리콘 활성층의 채널영역과 쇼트키접합(schottky junction)을 형성하도록 소스 및 드레인 전극을 금속실리사이드로 형성하는 단계 및 상기 소스 및 드레인 전극을 촉매로 하여 상기 채널영역의 비정질실리콘을 폴리실리콘으로 결정화시키는 단계를 포함하고 있으며, 이를 통하여 공정과정을 단순화시킬 수 있으며, 공정비용을 절감할 수 있는 효과가 있다.
비정질실리콘, 폴리실리콘, 쇼트키장벽, 박막트랜지스터, 결정화-
Patent Agency Ranking
公开(公告)号：KR100881956B1
公开(公告)日：2009-02-06
申请号：KR1020070108057
申请日：2007-10-26
Applicant: 한국전자통신연구원
IPC: G01N33/48
CPC classification number: B01J19/0046 , B01J2219/00283 , B01J2219/00351 , B01J2219/00475 , B01J2219/00529 , B01J2219/00533 , B01J2219/00596 , B01J2219/00605 , B01J2219/00659 , B01J2219/00691 , B01L9/52
Abstract: A biochemistry sensor surface treating apparatus is provided to mass produce a sensor by performing a process of surface-processing the sensor by using automatized apparatus. A biochemistry sensor surface treating apparatus contains one or more containers(216) putting one sample of chemical substance, biochemical substance and biomass which are samples surface-processed at one-side of chip used as a biochemistry sensor; a chip off-loading unit(224) having size inserted inside the container for surface process of chip; one or more process areas(210,230) containing a changeable transfer frame(214) changed along X-Y-Z shafts for surface-processing the chip. A first engaging portion attaching/detaching the chip off-loading unit is equipped at a bottom of the Z-shaft.
Abstract translation: 提供了一种生化传感器表面处理装置，通过使用自动化装置进行表面处理传感器的处理来大量生产传感器。 生物传感器表面处理装置包含一个或多个容器（216），将一个样品的化学物质，生化物质和生物质样品在用作生物化学传感器的芯片的一侧进行表面处理; 芯片卸载单元（224），其尺寸插入到用于芯片表面处理的容器内; 一个或多个包含可更换传送框架（214）的处理区域（210,230）沿X-Y-Z轴改变，以对芯片进行表面处理。 安装/拆卸芯片卸载单元的第一接合部分设置在Z轴的底部。
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107.发明公开
公开(公告)号：KR1020080052294A
公开(公告)日：2008-06-11
申请号：KR1020070082205
申请日：2007-08-16
Applicant: 한국전자통신연구원
CPC classification number: G01N33/5308 , C12Q1/6825 , G01N33/54313 , G01N33/54393 , Y10T436/143333 , B82Y15/00
Abstract: Substrates for analyzing the coverage of self-assembled molecules are provided to measure efficiently the presence and reaction degree of functional groups on the surface of self-assembled molecules by using nanoparticles without use of complicated methods such as FT-IR(Fourier Transform InfraRed), XPS(X-ray photoelectron spectroscopy) and fluorescence method. A substrate for analyzing the coverage of self-assembled molecules comprises: a substrate(100) for immobilizing biomaterials; a self-assembled molecule layer(102) formed on the substrate and having a functional group capable of reacting with an amine group; a capture DNA molecule(200) having the amine group to be combined with the self-assembled molecule layer; and a probe DNA molecule combining with the capture DNA molecule and having nanoparticles on the surface, wherein the functional group capable of reacting with an amine group is -SH, -NH2, -Si(OCH3)3, -Si(OC2H5)3 and -Si(Cl)3. Further, the substrate(100) for immobilizing biomaterial is one selected from a group consisting of glass, polycarbonate, polyester, polyethylene, polypropylene and wafer.
Abstract translation: 提供用于分析自组装分子覆盖的底物，通过使用纳米粒子，有效地测量自组装分子表面官能团的存在和反应程度，而不使用复杂的方法，如FT-IR（傅立叶变换红外） XPS（X射线光电子能谱）和荧光法。 用于分析自组装分子的覆盖的基板包括：用于固定生物材料的基底（100）; 形成在所述基板上并具有能够与胺基反应的官能团的自组装分子层（102）; 具有与自组装分子层结合的胺基的捕获DNA分子（200）; 和与捕获DNA分子结合并在表面上具有纳米颗粒的探针DNA分子，其中能与胺基反应的官能团为-SH，-NH2，-Si（OCH3）3，-Si（OC2H5）3和 -Si（CL）3。 此外，用于固定生物材料的基板（100）选自由玻璃，聚碳酸酯，聚酯，聚乙烯，聚丙烯和晶片组成的组中的一种。
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公开(公告)号：KR1020070059880A
公开(公告)日：2007-06-12
申请号：KR1020060059128
申请日：2006-06-29
Applicant: 한국전자통신연구원
CPC classification number: H01L21/02601 , B82Y15/00 , H01L21/02554 , H01L21/28 , H01L21/30604 , H01L21/7806 , H01L29/0665 , H01L29/413
Abstract: A process for fabrication of a sensor having a nano-gap electrode is provided to form the sensor with excellent sensitivity compared to common detective sensors and to ensure integration and massive production of sensor devices by forming a laminate structure of metal electrode layer and intermediate oxide layer and adopting the structure for the nano-gap electrode sensor. The process includes the steps of: (a) partitioning top side of an oxide layer into first, second and third regions; (b) forming first metal electrode layer(20,60) on the first and second regions and preparing an intermediate oxide layer over the first metal electrode layer; (c) forming second metal electrode layer(40,80) on the first and third regions and preparing another intermediate oxide layer over the second metal electrode layer; (d) repeatedly performing the steps of (b) and (c) to laminate multiple metal electrode layers and the intermediate layers(30,50,70); (e) forming multiple channels to pass through all of the metal electrode layers and the intermediate layers; and (h) partially etching the intermediate oxide layers to form nano-gaps between the first and second metal electrode layers.
Abstract translation: 提供了具有纳米间隙电极的传感器的制造方法，以与常见的检测传感器相比形成具有优异灵敏度的传感器，并且通过形成金属电极层和中间氧化物层的层叠结构来确保传感器装置的集成和大量生产 并采用纳米间隙电极传感器的结构。 该方法包括以下步骤：（a）将氧化物层的顶侧划分成第一，第二和第三区域; （b）在第一和第二区域上形成第一金属电极层（20,60），并在第一金属电极层上制备中间氧化物层; （c）在第一和第三区域上形成第二金属电极层（40,80），并在第二金属电极层上制备另一个中间氧化物层; （d）重复执行步骤（b）和（c）以层叠多个金属电极层和中间层（30,50,70）; （e）形成多个通道以通过所有金属电极层和中间层; 和（h）部分地蚀刻中间氧化物层以在第一和第二金属电极层之间形成纳米间隙。
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公开(公告)号：KR100659581B1
公开(公告)日：2006-12-20
申请号：KR1020050119225
申请日：2005-12-08
Applicant: 한국전자통신연구원
IPC: C30B29/06
Abstract: A method for crystallizing silicon, a thin film transistor manufactured by the same, and its manufacturing method are provided to improve electron mobility of the thin film transistor by metal-catalyst-induced crystallization. A crystalline filter(120) is formed on a substrate(100). A metal catalyst layer(130) is formed in the crystalline filter. A resist pattern having holes is formed on the substrate. The substrate is patterned along the resist pattern to form the crystalline filter of a well structure. An amorphous silicon layer(140) is deposited on the whole substrate including the crystalline filter. The substrate is thermally processed to crystallize the amorphous silicon layer by metal-catalyst-induced crystallization, so that electron mobility of a thin film transistor is improved.
Abstract translation: 提供一种用于使硅结晶的方法及由其制造的薄膜晶体管及其制造方法，以通过金属 - 催化剂诱导的结晶来改善薄膜晶体管的电子迁移率。 晶体滤波器（120）形成在衬底（100）上。 金属催化剂层（130）形成在晶体滤波器中。 在基板上形成具有孔的抗蚀剂图案。 沿着抗蚀剂图案图案化衬底以形成阱结构的晶体滤波器。 在包括晶体滤波器的整个基板上沉积非晶硅层（140）。 对基板进行热处理以通过金属 - 催化剂诱导的结晶使非晶硅层结晶，从而提高薄膜晶体管的电子迁移率。
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公开(公告)号：KR100601053B1
公开(公告)日：2006-07-19
申请号：KR1020050034030
申请日：2005-04-25
Applicant: 한국전자통신연구원
IPC: H01L21/336
Abstract: 충돌 이온화를 이용한 트랜지스터 및 그 제조 방법을 제시한다. 본 발명에 따르면, 반도체 기판 상에 게이트 유전막, 게이트 및 제1 및 제2 측벽 스페이서를 형성하고, 반도체 기판에 불순물을 경사 이온 주입하여 게이트 및 제1 및 제2스페이서에 마스킹(masking)되어 제1스페이서로부터 이격된 제1불순물층 및 제2스페이서 아래에 중첩되게 연장된 제2불순물층을 형성한다. 상호 간의 사이의 반도체 기판 영역을 이온화 영역으로 설정하는 소스 및 드레인을 제1 및 제2스페이서에 각각 자기 정렬되게 반도체 기판 상에 형성한다. 이때, 소스가 이온화 영역과 쇼트키 접합(schottky junction)을 이루게 제1금속 실리사이드막을 포함하여 형성되고, 드레인이 제2스페이서 아래에 중첩되는 제2불순물층 부분 및 제2불순물층 영역과 저항성 접촉(ohmic contact)을 이루게 제2스페이서에 정렬되는 제2실리사이드막을 포함하여 형성된다.
충돌 이온화, 애벌랜치 항복, 실리사이드, 쇼트키 장벽, 비대칭 소스 드레인
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