公开(公告)号：JPWO2009044901A1

公开(公告)日：2011-02-17

申请号：JP2009536127

申请日：2008-10-04

Applicant: 国立大学法人京都大学

Inventor： 孝明 鈴木 ,  孝明 鈴木 ,  秀俊 小寺 ,  秀俊 小寺 ,  神野　伊策 ,  伊策 神野

IPC: B01J19/00 ,  B29C67/00 ,  B81B1/00 ,  B81C99/00 ,  C12M1/00 ,  G01N35/08 ,  G01N37/00

CPC classification number: B81C1/00103 ,  B29C35/0894 ,  B81B2201/058 ,  B81C2201/0159 ,  G03F7/201

Abstract: 複数部品の位置合せなしに簡単にかつ高精度に微小構造体を作製することができる、微小構造体の形成方法を提供する。(1)マスクパターン及び光硬化性樹脂を貫通する一つの回転軸を中心に回転させながら、回転軸に対して斜め方向からマスクパターンを介して光硬化性樹脂の露光を行い、光硬化性樹脂の露光部分に、光硬化性樹脂が硬化する吸光量の閾値である硬化基準値以上の吸光量になった高露光部分と硬化基準値未満の吸光量である低露光部分とを含む吸光量分布を形成する第1のステップと、(2)光硬化性樹脂の高露光部分の少なくとも一部により微小構造体の少なくとも一部を形成する第2のステップとを備える。

公开(公告)号：JP2010219523A

公开(公告)日：2010-09-30

申请号：JP2010046387

申请日：2010-03-03

Applicant: Commissariat A L'energie Atomique & Aux Energies Alternatives ,  コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ

Inventor： LANDIS STEFAN

IPC: H01L21/027 ,  B29C33/38 ,  B29C59/02 ,  B81C1/00

CPC classification number: G03F7/2059 ,  B81C99/009 ,  B81C2201/0159 ,  B81C2201/034 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/0017

Abstract: PROBLEM TO BE SOLVED: To provide a lithography technique used to fabricate a positive-type imprint. SOLUTION: The invention concerns a device where imprint molds are formed in three dimensions and includes: at least a substrate which is provided with at least one alternate layers each having at least one portion perpendicular to its top surface, the alternate layers each consisting of a first-type material or a second-type material allowed to be selectively etched with respect to each other; and a surface topology which has (a) at least the first patterns whose top lies at the first level relative to the top surface of the substrate located at either side of the topology, and these first patterns are made of the first-type material and (b) at least the second patterns which have at least the second level relative to the top surface of the substrate and are different from and lower than the first level, and these second patterns are made of the second-type material. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供用于制造正型印记的光刻技术。 解决方案：本发明涉及一种设备，其中压印模具以三维形成，并且包括：至少一个衬底，其设置有至少一个交替层，每层具有垂直于其顶表面的至少一个部分，每个替代层 由允许相对于彼此选择性蚀刻的第一类型材料或第二类型材料组成; 以及表面拓扑结构，其具有（a）至少第一图案，其顶部相对于位于拓扑结构的任一侧的基板的顶表面位于第一水平处，并且这些第一图案由第一类型材料制成，并且 （b）至少第二图案，其相对于基板的顶表面至少具有第二级，并且与第一级不同且低于第一级，并且这些第二图案由第二类型材料制成。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2004066451A

公开(公告)日：2004-03-04

申请号：JP2003325030

申请日：2003-09-17

Applicant: Wisconsin Alumni Res Found ,  ウィスコンシン アラムニ リサーチ ファンデーション

Inventor： GUCKEL HENRY ,  CHRISTENSON TODD R ,  SKROBIS KENNETH

IPC: G03F7/027 ,  B81B1/00 ,  B81C1/00 ,  G03F7/00 ,  G03F7/20 ,  G03F7/26 ,  G03F7/30 ,  G03F7/38 ,  G03F7/40 ,  H01L21/027 ,  H05K3/18

CPC classification number: G03F7/38 ,  B81C1/0038 ,  B81C2201/0128 ,  B81C2201/0159 ,  B81C2201/019 ,  B81C2201/032 ,  G03F7/00 ,  G03F7/0035 ,  Y10S430/168 ,  Y10T428/31504

Abstract: PROBLEM TO BE SOLVED: To provide a micromechanical structure body or a laminated body having an RMMA thin layer having no internal distortion and excellent in vertical characteristics of a wall.
SOLUTION: The michromechanical structure body includes an independent RMMA main body wherein at least one of an upper surface or a lower surface is mechanically rolled, and a thickness between the upper surface and the lower surface is smaller than 1 mm. The main body is produced by preformed PMMA substantially having no internal stress. The laminated body includes the low-molecular weight PMMA thin layer on a surface of a substrate, and a preformed PMMA sheet having a thickness of less than 3 mm and bonded on the low-molecular weight PMMA layer by a function of a solvent. The laminated layer body is prepared by spin coating the substrate with the low-molecular weight PMMA thin layer, curing the layer, wetting the low-molecular weight PMMA layer with an MMA monomer, applying the PMMA preformed sheet for the wetted layer, bonding the preformed sheet on the wetted layer, and bonding the preformed sheet on the substrate.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP3366405B2

公开(公告)日：2003-01-14

申请号：JP30678493

申请日：1993-12-07

Applicant: ウィスコンシン アラムニ リサーチ ファンデーション

Inventor： スコロビス ケニス ,  アール クリステンソン トッド ,  グッケル ヘンリー

IPC: G03F7/027 ,  B81B1/00 ,  B81C1/00 ,  G03F7/00 ,  G03F7/20 ,  G03F7/26 ,  G03F7/30 ,  G03F7/38 ,  G03F7/40 ,  H01L21/027 ,  H05K3/18

CPC classification number: G03F7/38 ,  B81C1/0038 ,  B81C2201/0128 ,  B81C2201/0159 ,  B81C2201/019 ,  B81C2201/032 ,  G03F7/00 ,  G03F7/0035 ,  Y10S430/168 ,  Y10T428/31504

公开(公告)号：US20240174512A1

公开(公告)日：2024-05-30

申请号：US17994471

申请日：2022-11-28

Applicant: TAIWAN MASK CORPORATION

Inventor： SHANG-KUANG WU ,  YU-TSUNG FU ,  MING-WEI HUANG

IPC: B81C1/00

CPC classification number: B81C1/00055 ,  B81C2201/0133 ,  B81C2201/0142 ,  B81C2201/0159

Abstract: A MEMS probe and manufacturing method thereof are provided. The method is mainly to form connected first-level, second-level, and third-level pin grooves on both sides of the silicon substrate through an etching process, followed by two electroplating processes to deposit nickel-cobalt-phosphorus alloy in the first-level pin groove to form the tip of the microprobe, and to deposit nickel-cobalt alloy in the second-level pin groove and the third-level pin to form the pin head and pin arm, thereby forming a three-level microprobe. A circuit substrate made of ceramic material is disposed with at least one window, the surface of the circuit substrate adjacent to the window is provided with a plurality of circuit pads, and the circuit substrate is abutted to the pin arm of the microprobe. The silicon substrate is then removed, to form a plurality of cantilever microprobes made of nickel-cobalt-phosphorus alloy and nickel-cobalt alloy on the circuit substrate.

公开(公告)号：US11903139B2

公开(公告)日：2024-02-13

申请号：US17181756

申请日：2021-02-22

Applicant: CARNEGIE MELLON UNIVERSITY

Inventor： Carmel Majidi ,  Burak Ozdoganlar ,  Arya Tabatabai ,  Bulent Arda Gozen

IPC: H05K3/10 ,  H05K1/02 ,  G03F7/00 ,  H05K3/28 ,  H05K1/16

CPC classification number: H05K3/107 ,  G03F7/0002 ,  H05K1/0283 ,  B81C2201/0156 ,  B81C2201/0159 ,  H05K1/162 ,  H05K3/281 ,  H05K2201/0162 ,  H05K2201/10015 ,  H05K2203/0108 ,  H05K2203/0156

Abstract: The disclosure describes a soft-matter electronic device having micron-scale features, and methods to fabricate the electronic device. In some embodiments, the device comprises an elastomer mold having microchannels, which are filled with an eutectic alloy to create an electrically conductive element. The microchannels are sealed with a polymer to prevent the alloy from escaping the microchannels. In some embodiments, the alloy is drawn into the microchannels using a micro-transfer printing technique. Additionally, the molds can be created using soft-lithography or other fabrication techniques. The method described herein allows creation of micron-scale circuit features with a line width and spacing that is an order-of-magnitude smaller than those previously demonstrated.

公开(公告)号：US20230236517A1

公开(公告)日：2023-07-27

申请号：US18130328

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Changhua LIU ,  Jianyong MO ,  Liang ZHANG

IPC: G03F7/20 ,  B81B1/00 ,  B81C1/00

CPC classification number: G03F7/70733 ,  B81B1/00 ,  B81C1/00111 ,  G03F7/201 ,  B81B2203/0361 ,  B81C2201/0159

Abstract: Embodiments disclosed herein include lithographic patterning systems for non-orthogonal patterning and devices formed with such patterning. In an embodiment, a lithographic patterning system comprises an actinic radiation source, where the actinic radiation source is configured to propagate light along an optical axis. In an embodiment, the lithographic patterning system further comprises a mask mount, where the mask mount is configurable to orient a surface of a mask at a first angle with respect to the optical axis. In an embodiment, the lithographic patterning system further comprises a lens module, and a substrate mount, where the substrate mount is configurable to orient a surface of a substrate at a second angle with respect to the optical axis.

公开(公告)号：US20180148324A1

公开(公告)日：2018-05-31

申请号：US15725752

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Han MENG ,  Chih-Hsien HSU ,  Chia-Chi CHUNG ,  Yu-Pei CHIANG ,  Wen-Chih CHEN ,  Chen-Huang HUANG ,  Zhi-Sheng XU ,  Jr-Sheng CHEN ,  Kuo-Chin LIU ,  Lin-Ching HUANG

IPC: B81C1/00 ,  H01H59/00 ,  H01G5/18 ,  B81B3/00

CPC classification number: B81C1/00182 ,  B81B3/0072 ,  B81C1/00158 ,  B81C1/00476 ,  B81C1/00523 ,  B81C2201/0159 ,  B81C2201/0198 ,  H01G5/18 ,  H01H59/0009

Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a second substrate over a first substrate, and a cavity is formed between the first substrate and the second substrate. The method includes forming a hole through the second substrate using an etching process, and the hole is connected to the cavity. The etching process includes a plurality of etching cycles, and each of the etching cycles includes an etching step, and the etching step has a first stage and a second stage. The etching time of each of the etching steps during the second stage is gradually increased as the number of etching cycles is increased.

公开(公告)号：US09975761B2

公开(公告)日：2018-05-22

申请号：US15444086

申请日：2017-02-27

Applicant: SMARTTIP BV

Inventor： Edin Sarajlic

IPC: B81C1/00 ,  A61B5/15

CPC classification number: B81C1/0015 ,  A61B5/150022 ,  A61B5/150282 ,  A61B5/150396 ,  A61B5/150511 ,  A61B5/150519 ,  A61B5/150984 ,  A61B5/15142 ,  A61M37/0015 ,  B81B2201/057 ,  B81B2201/12 ,  B81B2203/0118 ,  B81B2203/0353 ,  B81C1/00087 ,  B81C1/00111 ,  B81C1/00119 ,  B81C2201/0132 ,  B81C2201/0143 ,  B81C2201/0159 ,  B81C2201/0198 ,  C01B21/0687

Abstract: A method of manufacturing a plurality of through-holes in a layer of first material, for example for the manufacturing of a probe comprising a tip containing a channel. To manufacture the through-holes in a batch process, a layer of first material is deposited on a wafer comprising a plurality of pits a second layer is provided on the layer of first material, and the second layer is provided with a plurality of holes at central locations of the pits; using the second layer as a shadow mask when depositing a third layer at an angle, covering a part of the first material with said third material at the central locations, and etching the exposed parts of the first layer using the third layer as a protective layer.

公开(公告)号：US20170166443A1

公开(公告)日：2017-06-15

申请号：US15197418

申请日：2016-06-29

Applicant: HYUNDAI MOTOR COMPANY

Inventor： Ilseon YOO

IPC: B81C1/00

CPC classification number: B81C1/00269 ,  B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/04 ,  B81C2201/013 ,  B81C2201/0159 ,  B81C2203/0118 ,  B81C2203/031 ,  B81C2203/035 ,  B81C2203/036

Abstract: A manufacturing method of a MEMS sensor includes forming a first substrate, wherein the first substrate includes a lower electrode provided at one surface thereof, forming a second substrate, wherein the second substrate includes a first concave-convex portion provided at one surface thereof, first-bonding one surface of the first substrate and one surface of the second substrate to face each other, forming a third substrate, wherein the third substrate includes an upper electrode provided at one surface thereof, second-bonding another surface of the second substrate and one surface of the third substrate to face each other, and forming an electrode line on another surface of the third substrate to be connected to the lower electrode and the upper electrode.