公开(公告)号：US3698940A

公开(公告)日：1972-10-17

申请号：US3698940D

申请日：1970-01-26

Applicant: MACDERMID INC

Inventor： MERSEREAU MARK ,  RHODENIZER HAROLD L ,  GRUNWALD JOHN J ,  INNES WILLIAM P

IPC: C23C18/16 ,  C23C18/20 ,  H05K3/06 ,  H05K3/10 ,  H05K3/18 ,  H05K3/38 ,  B44D1/18

CPC classification number: C23C18/1653 ,  C23C18/1605 ,  C23C18/2086 ,  H05K3/062 ,  H05K3/108 ,  H05K3/181 ,  H05K3/38 ,  H05K3/381 ,  H05K2201/0344 ,  H05K2203/0783 ,  H05K2203/1105 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A METHOD IS DISCLOSED FOR FORMING PRINTED CIRCUIT BOARDS BY THE ADDITIVE PROCESS, IN WHICH THE SURFACE OF THE SUBSTRATE IS CONTACTED WITH A PARTICULAR CLASS OF SOLVENTS, PRIOR TO ELECTROLESS DEPOSITION OF THE METAL THEREON,

AND AT ONE OR MORE POINTS IN THE PROCESS THE BOARD IS HEATED OR BAKED.

公开(公告)号：US3306830A

公开(公告)日：1967-02-28

申请号：US28755263

申请日：1963-06-13

Applicant: BELL TELEPHONE LABOR INC

Inventor： GUSTAV BITTRICH ,  EHRHARDT ROBERT A

IPC: C23C18/16 ,  C23C18/36 ,  H05K3/06 ,  H05K3/10 ,  H05K3/18 ,  H05K3/42

CPC classification number: H05K3/426 ,  C23C18/1605 ,  C23C18/1653 ,  C23C18/1689 ,  C23C18/36 ,  H05K3/062 ,  H05K3/108 ,  H05K3/181 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2203/0723

公开(公告)号：US3269861A

公开(公告)日：1966-08-30

申请号：US28963363

申请日：1963-06-21

Applicant: DAY COMPANY

Inventor： SCHNEBLE JR FREDERICK W ,  JOHN ZEBLISKY RUDOLPH ,  FRANCIS MCCORMACK JOHN ,  DUFF WILLIAMSON JOHN

IPC: C07F1/00 ,  C23C18/16 ,  C23C18/40 ,  H05K3/00 ,  H05K3/06 ,  H05K3/10 ,  H05K3/18 ,  H05K3/42

CPC classification number: H05K3/187 ,  C07F1/005 ,  C23C18/1605 ,  C23C18/405 ,  H05K3/0094 ,  H05K3/064 ,  H05K3/108 ,  H05K3/422 ,  H05K3/427 ,  H05K3/428 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09581 ,  H05K2203/0565 ,  H05K2203/072 ,  H05K2203/1383 ,  H05K2203/1423

公开(公告)号：US3154478A

公开(公告)日：1964-10-27

申请号：US69430357

申请日：1957-11-04

Applicant: GEN AM TRANSPORT

Inventor： LEE WARREN G

IPC: C23C18/30 ,  C23C18/36 ,  H05K3/10 ,  H05K3/18 ,  H05K3/24 ,  H05K3/42

CPC classification number: H05K3/244 ,  C23C18/30 ,  C23C18/36 ,  H05K3/108 ,  H05K3/187 ,  H05K3/426 ,  H05K2201/0344 ,  Y10T29/49155

公开(公告)号：US3090706A

公开(公告)日：1963-05-21

申请号：US82539059

申请日：1959-07-03

Applicant: MOTOROLA INC

Inventor： CADO ERWIN E

IPC: C09D167/00 ,  C23C2/02 ,  H05K3/28 ,  H05K3/34 ,  H05K3/42

CPC classification number: C23C2/02 ,  C09D167/00 ,  H05K3/282 ,  H05K3/285 ,  H05K3/3452 ,  H05K3/426 ,  H05K2201/0344 ,  Y10S428/901 ,  Y10T29/49124 ,  Y10T428/24802 ,  Y10T428/24851 ,  Y10T428/24917

公开(公告)号：US3061911A

公开(公告)日：1962-11-06

申请号：US71235558

申请日：1958-01-31

Applicant: XEROX CORP

Inventor： MITCHELL BAKER

IPC: H05K1/16 ,  H05K3/06 ,  H05K3/18

CPC classification number: H05K1/167 ,  H05K3/067 ,  H05K3/181 ,  H05K2201/0317 ,  H05K2201/0326 ,  H05K2201/0344 ,  Y10T29/49099 ,  Y10T29/49156

公开(公告)号：US20160242285A1

公开(公告)日：2016-08-18

申请号：US15044380

申请日：2016-02-16

Applicant: IBIDEN CO., LTD.

Inventor： Takayuki Katsuno ,  Yuki Ito ,  Takeshi Furusawa ,  Takema Adachi

IPC: H05K1/11 ,  H05K1/09

CPC classification number: H05K1/0271 ,  H05K3/007 ,  H05K3/025 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/098 ,  H05K2203/1184

Abstract: A printed wiring board includes a resin insulating layer having recess portions formed on first surface, a first conductor layer formed in the recess portions and including pads positioned to mount an electronic component, conductive pillars formed on the pads, respectively, and formed to mount the electronic component onto the resin insulating layer, a second conductor layer formed on second surface of the resin insulating layer on the opposite side with respect to the first surface, and a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer and connecting the first and second conductor layers. The pillars is formed such that each of the pads has an exposed surface exposed from a respective one of the conductive pillars, and the pads are formed such that the exposed surface is recessed from the first surface of the resin insulating layer.

Abstract translation: 印刷电路板包括具有形成在第一表面上的凹部的树脂绝缘层，形成在凹部中的第一导体层，并且包括分别安装电子部件的焊盘，形成在焊盘上的导电柱，并形成为安装 电子部件到树脂绝缘层上，在相对于第一表面的相对侧的树脂绝缘层的第二表面上形成的第二导体层和形成在树脂绝缘层中的通孔导体，使得通孔导体穿透 树脂绝缘层并连接第一和第二导体层。 柱形成为使得每个焊盘具有从相应的一个导电柱露出的暴露表面，并且焊盘被形成为使得暴露的表面从树脂绝缘层的第一表面凹陷。

公开(公告)号：US09414500B2

公开(公告)日：2016-08-09

申请号：US13320285

申请日：2010-05-27

Applicant: James Rathburn

Inventor： James Rathburn

IPC: H05K3/12 ,  H01L23/498 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H05K1/02 ,  H05K1/16 ,  H05K3/10 ,  H05K3/20 ,  H05K3/24 ,  H05K3/28

CPC classification number: H05K1/181 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/0221 ,  H05K1/0256 ,  H05K1/0274 ,  H05K1/0284 ,  H05K1/118 ,  H05K1/16 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/207 ,  H05K3/246 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4664 ,  H05K3/4694 ,  H05K2201/0344 ,  H05K2201/0367 ,  H05K2201/09109 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T29/49155

Abstract: A compliant printed flexible circuit including a flexible polymeric film and at least one dielectric layer bonded to the polymeric film with recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the recesses to form a circuit geometry. At least one dielectric covering layer is printed over at least the circuit geometry. Openings can be printed in the dielectric covering layer to provide access to at least a portion of the circuit geometry.

Abstract translation: 包括柔性聚合物膜和柔性聚合物膜的柔性印刷柔性电路以及与聚合物膜结合的至少一个介电层，其具有对应于目标电路几何形状的凹部。 在至少一部分凹部中印刷导电材料以形成电路几何形状。 至少一个电介质覆盖层至少印刷在电路几何形状上。 开口可以印刷在电介质覆盖层中以提供对电路几何形状的至少一部分的访问。

公开(公告)号：US09320153B2

公开(公告)日：2016-04-19

申请号：US14548725

申请日：2014-11-20

Applicant: IBIDEN CO., LTD.

Inventor： Masahiro Kaneko ,  Satoru Kose ,  Hirokazu Higashi

IPC: H05K3/02 ,  H05K3/10 ,  H05K3/42 ,  H01L21/683 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H05K1/11 ,  H05K1/03 ,  H05K3/22 ,  H05K3/00 ,  H05K3/38

CPC classification number: H05K3/42 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0313 ,  H05K1/113 ,  H05K1/115 ,  H05K3/007 ,  H05K3/108 ,  H05K3/22 ,  H05K3/388 ,  H05K2201/0344 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/1377 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed wiring board includes an interlayer resin insulation layer having a penetrating hole, a conductive circuit formed on a first surface of the interlayer resin insulation layer, a filled via conductor formed in the penetrating hole of the interlayer resin insulation layer and connected to the conductive circuit, a first surface-treatment coating structure formed on a first surface of the filled via conductor and having an electroless plating structure, and a second surface-treatment coating structure formed on a second surface of the filled via conductor on an opposite side with respect to the first surface-treatment coating structure and having an electroless plating structure. The filled via conductor includes a first conductive layer formed on side wall of the penetrating hole and a plated material filling the penetrating hole, and the first surface-treatment coating structure has a thickness which is different from a thickness of the second surface-treatment coating structure.

Abstract translation: 印刷电路板包括具有贯通孔的层间树脂绝缘层，形成在层间树脂绝缘层的第一表面上的导电电路，形成在层间树脂绝缘层的穿透孔中并与导电 电路，形成在填充的通路导体的第一表面上并具有无电解电镀结构的第一表面处理涂层结构和形成在填充通孔导体的第二表面上的第二表面处理涂层结构，该第二表面处理涂层结构相对于 涉及第一表面处理涂层结构并具有化学镀层结构。 填充的通孔导体包括形成在穿透孔的侧壁上的第一导电层和填充穿透孔的电镀材料，第一表面处理涂层结构的厚度与第二表面处理涂层的厚度不同 结构体。

公开(公告)号：US08992756B2

公开(公告)日：2015-03-31

申请号：US12513611

申请日：2006-11-06

Applicant: Hisamitsu Yamamoto

Inventor： Hisamitsu Yamamoto

IPC: C25D5/02 ,  C23C18/44 ,  C25D5/56 ,  H05K3/18 ,  H05K3/42 ,  C23C18/16 ,  C23C18/20 ,  C23C18/30 ,  H05K1/03

CPC classification number: C23C18/44 ,  C23C18/1653 ,  C23C18/2086 ,  C23C18/30 ,  C25D5/02 ,  C25D5/56 ,  H05K1/0346 ,  H05K3/181 ,  H05K3/422 ,  H05K3/427 ,  H05K2201/0344 ,  H05K2203/124

Abstract: A surface of an object to be plated is subjected to a treatment for palladium catalyst impartation to impart a palladium catalyst to the surface of an insulating part thereof. A palladium conductor layer is formed on the insulating part from a solution for palladium conductor layer formation which contains a palladium compound, an amine compound, and a reducing agent. On the palladium conductor layer is then directly formed a copper deposit by electroplating. Thus, the work is converted to a conductor with the solution for palladium conductor layer formation, which is neutral, without using an electroless copper plating solution which is highly alkaline. Consequently, the polyimide is prevented from being attacked and no adverse influence is exerted on adhesion. By adding an azole compound to the solution for palladium conductor layer formation, a palladium conductor layer is prevented from depositing on copper.

Abstract translation: 对被镀物体的表面进行钯催化剂的处理，将钯催化剂赋予其绝缘部分的表面。 在包含钯化合物，胺化合物和还原剂的钯导体层形成用溶液的绝缘部上形成钯导体层。 然后在钯导体层上通过电镀直接形成铜沉积物。 因此，不用使用高碱性化学镀铜溶液，将工件转化为具有中性的钯导体层形成溶液的导体。 因此，防止聚酰亚胺受到攻击，并且不会对粘合产生不利影响。 通过向溶液中添加唑化合物以形成钯导体层，可以防止钯导体层沉积在铜上。