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111.发明专利
公开(公告)号：JPH1075308A
公开(公告)日：1998-03-17
申请号：JP15127797
申请日：1997-06-09
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUN
Inventor： KUANNJIE CHON
Abstract: PROBLEM TO BE SOLVED: To send a voice message during a speech or during absence even when a general telephone network subscriber does not possess an automatic reply telephone set by storing a voice message to an intelligence information service system (IP). SOLUTION: When a local exchange LE recognizes an automatic telephone reply service request, an intelligent network service exchange (SSP) 104 triggers a service logic and makes a service request to a service controller (SCP) 101 and the IP 105 is used to make routing. The IP 105 is controlled by the SCP 101 through the SSP 104, serves a special resource to the service user and collects or stores input data from the service user. The SCP 101 has the service logic and data required for the service to control and process the automatic telephone reply service. A service management system(SMS) 102 revises and manages data and logic required to conduct the service. A signal repeater (STP) 103 sends an SSNo.7 message between the SCP 101 and the SSP 104.
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112.发明专利
公开(公告)号：JPH09237987A
公开(公告)日：1997-09-09
申请号：JP30185196
申请日：1996-11-13
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： JIESUPU HAN , KIYUSOPU SON , SUNCHIYURU KIMU , NAMUIRU HAA
Abstract: PROBLEM TO BE SOLVED: To provide a printed circuit board guide rail system which is provided with an ESD(electrostatic) preventive function and simple in structure so as to effectively protect a printed circuit board against damage caused by static electricity. SOLUTION: A ESD grounding plane 10 is formed on the one surface of a printed circuit board 4'. An engaging step 17 is projected at the lower end of a guide rail 5, and an insertion groove 13 where an ESD strip 8 which is formed by fending an ESD grounding plane contact 18 and an ESD printed circuit board contact 14 is inserted is provided in the side of the guide rail 5. The ESD strip 8 is inserted into the insertion groove 13. An ESD printed circuit board 7 provided with a copper foil 9 on its upside is provided in the side of a sub-rack through the intermediate of an insulator 12 traversing the rear lower end of the sub-rack 1 so as to be inserted into a groove provided in the engaging step 17 of the guide rail 5, and a grounding cable 11 is linked to both ends of the ESD printed circuit board 7.
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公开(公告)号：JPH09185024A
公开(公告)日：1997-07-15
申请号：JP22243996
申请日：1996-08-23
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： UORUYON UHAN , JIYANJIYOO KIMU
Abstract: PROBLEM TO BE SOLVED: To provide a Mach-Zehnder interferometer type polymer electro-optical modulator formed so as to remove or reduce a DC drift problem appearing on a light modulator by using the optical bleaching characteristic of polymer. SOLUTION: A lower electrode layer 312. a lower clading layer 113, a guiding layer 114, an initial optical bleaching layer 115, a later optical bleaching layer 117, an upper clading layer 118, and electrodes 119a, 119b are successively laminated on a semiconductor substrate 111. The initial state of the electro-optical modultor is controlled by forming the 1st and 2nd electrodes 119a, 119b having respectively different lengths on the upper side of 1st and 2nd arms 116b, 116c branched between the input terminal 116a and output terminal 116d of an waveguide 116 and then connected to each other again by using the later optical bleaching layer 117 as a mask.
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公开(公告)号：JPH09181713A
公开(公告)日：1997-07-11
申请号：JP31611296
申请日：1996-11-27
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： HIIYON JIYUN , BUMUCHIEORU RII , KUUONCHIYURU PAAKU
Abstract: PROBLEM TO BE SOLVED: To apply re-timing to data stably even when a static skew due to a difference of delay between a re-timing clock pulse and data bits and a dynamic skew due to a change in time and temperature are in existence in binary data bits sent at a high speed. SOLUTION: The device is provided with a means 201 generating nsets of multiple phase clock pulses with n-phases from an external input clock pulse, a means 202 providing an output of a control signal to select one clock pulse or over whose transition takes place close to the middle of an interval of data bits received externally among the n-sets of multiple phase clock pulses, a means '203 receiving the multiple phase clock pulses and a retiming clock pulse selection signal so as to synthesize the retiming clock pulses in a way that the transition of the re-timing clock pulse takes place in the middle of the interval of the data bits received externally, and a means 204 applying re-timing to externally received data by using the synthesized re-timing clock pulse.
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公开(公告)号：JPH09181570A
公开(公告)日：1997-07-11
申请号：JP21554496
申请日：1996-08-15
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： INDOUTSUKU UWAN
Abstract: PROBLEM TO BE SOLVED: To easily realize a monolithic microwave chip by providing the active orthogonal power distributor with an input impedance matching circuit, an FET to be turned on/off in accordance with the state of an output signal from the input impedance matching circuit, an output impedance matching circuit for outputting the output signal, and a reactive potential divider. SOLUTION: The output impedance matching circuit is a pi section type consisting of an inducator L3 and capacitors C2, C3 to an output terminal 1. The inductor L3 acts in parallel with an output terminal 2, an inductor L2 acts in series and the capacitors C2, C3 mutually connected in series act in parallel. A direct current(DC) is supplied from a power supply Vdd to an FET Q1 through the inductors L3, L2, a capacitor C5 is a by-pass capacitor and the inductor L3 is grounded like AC. Although the distributor has the same structure as a microwave amplifier, the distributor is also provided with two output terminal and the 90 deg. phase difference of output signals as compared with a conventional distributer.
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Patent Agency Ranking116.发明专利
公开(公告)号：JPH09181391A
公开(公告)日：1997-07-11
申请号：JP11265696
申请日：1996-05-07
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： HIIIYON CHIYUU , BIYUUNSUU YUU , HIYOOFUUN PAAKU , MINSUU PAAKU
Abstract: PROBLEM TO BE SOLVED: To control the polarizing direction of emitted light easily while sustaining the symmetry of oscillation beam from a vertical resonance surface emission laser diode by etching a resonance layer while inclining in the direction of or . SOLUTION: A lower mirror layer 2, an active layer 3 and an upper mirror layer 4 are formed sequentially on a GaAs substrate 1 and then a conductive metal is deposited and patterned to form an n-type electrode 5 followed by sequential deposition of Au, as an etching substance, by 1000-5000Å and Ni by 500-2000Å. It is then patterned to form a metal mask pattern 6, i.e., an etching mask for underlying part forming substance, and an exposed upper mirror layer 4 and active layer 3 are subjected to reactive ion etching or ion beam etching while inclining by 5-45 in the direction or . According to the method, the polarizing direction can be determined by a simple method without causing significant deviation of the oscillation beam of laser diode from circular symmetry.
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公开(公告)号：JPH09181364A
公开(公告)日：1997-07-11
申请号：JP19445296
申请日：1996-07-24
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： JIEONDE SUU , GANYAN SON
Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing an a-axis vertically orientated josephson junction device. SOLUTION: An oxide single crystal substrate 1 is thermally treated at a temperature of 800 to 850 deg.C, and a first oxide normal conductive thin film 2 is formed thereon at a temperature of 630 to 650 deg.C. A first high-temperature superconductive thin film 3 is formed on the normal conductive thin film 2 at a temperature of 750 to 770 deg.C, an oxide insulating thin film 4 is formed thereon at a temperature of 550 to 600 deg.C, a second oxide normal conductive thin film 5 is formed thereon at a temperature of 630 to 650 deg.C, and a second high-temperature superconductive thin film 6 is formed on the normal conductive thin film 5 at a temperature of 750 to 770 deg.C.
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公开(公告)号：JPH09181331A
公开(公告)日：1997-07-11
申请号：JP19342396
申请日：1996-07-23
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： KIYONWAN PAAKU , SEOONJIE RII , MINCHIEORU SHIN
IPC: H01L29/68 , H01L21/334 , H01L29/06 , H01L29/12 , H01L29/205 , H01L29/66 , H01L29/772 , H01L29/778 , H01L29/80
Abstract: PROBLEM TO BE SOLVED: To provide a plane resonance tunnel transistor of a structure, wherein the transistor has a high negative resistance and an adjustment of a resonance tunnel current is possible by an adjustment of a gate voltage. SOLUTION: Three potential barriers are formed by applying a negative voltage to fine isolation gates 2, 4, 6, (a) and (b). Thereby, two parts of asymmetrical zero dimension regions, that is, two asymmetrical quantum points are formed. A forward voltage is applied to both terminals 18 to contrive so as to cause two times of resonance tunnel phenomenons in a sequential manner. Moreover, the height of the third potential barrier is made low. By the two times of these sequential resonance tunnel phoenomemon a and the lowering of the height of the third pottential barrier, a resonance tunnel current can be outputted at the maximum value.
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公开(公告)号：JPH09181294A
公开(公告)日：1997-07-11
申请号：JP24790396
申请日：1996-09-19
Applicant: KOREA ELECTRONICS TELECOMM
Inventor： GIYUNOTSUKU KIMU , DONWAN ROU
IPC: H01L29/68 , H01L29/06 , H01L29/66 , H01L29/737 , H01L29/772
Abstract: PROBLEM TO BE SOLVED: To increase a PVR and a peak current using double resonant interband tunnelling hot electronic effect by a method wherein this electronic device is composed of a conductive emitter layer, a conductive collector layer, a conductive base layer, a collector barrier layer and an emitter electron injection layer. SOLUTION: A conductive collector layer 2 and an undoped collector barrier layer 3, located between a conductive base layer 4 and the conductive collector layer 2, are formed on a substrate 1. A quantum well structure, having the lowerst level of conductive band lower than a conductive emitter layer 6 and the conductive collector layer 2, is formed, and a conductive base layer 4 of the material of high electron mobility can be formed. Besides, an emitter electron implantation barrier layer 5, having emitter potential barrier layer structure between the conductive emitter layer 6 and the conductive base layer 4, and a conductive emitter layer 6 are formed. As a result, a peak to valley ratio(PVR) can be increased by the increase of a peak current due to the double resonant turnnelling effect.
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公开(公告)号：JPH09181090A
公开(公告)日：1997-07-11
申请号：JP26173796
申请日：1996-10-02
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Inventor： BIYUN RIYURU RIYUU , TE HIYON HAN , DOKU HO CHIYOO , SUU MIN RII , KUAN YUI PIYUN
IPC: H01L29/73 , H01L21/331 , H01L29/165 , H01L29/732 , H01L29/737
Abstract: PROBLEM TO BE SOLVED: To reduce resistance and increase the maximum oscillation frequency by etching a first insulating film exposed on an emitter, forming a conductive layer, applying an insulating layer to form contact holes, and then implementing a metal wiring process. SOLUTION: Polycrystalline silicon 21 of negative or positive conductivity type is evaporated, and then impurities are implanted. A pattern is formed to obtain an emitter electrode. In order to form a base electrode and a collector electrode, a nitride film 16, metallic silicate 15, a nitride film 14 and silicon/ silicon germanium 13 above a N sinker 12 are sequentially removed by dry etching. Thus the metallic silicate film is used as a non-active base electrode. This reduces the resistance of transmission lines and increases the maximum oscillation frequency.
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